From patchwork Thu Mar 1 09:48:39 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastian Hecht X-Patchwork-Id: 143975 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 22D2A1007D3 for ; Thu, 1 Mar 2012 20:51:04 +1100 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1S32e1-0003il-Bu; Thu, 01 Mar 2012 09:49:53 +0000 Received: from mail-ey0-f177.google.com ([209.85.215.177]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1S32da-0003Uj-2r for linux-mtd@lists.infradead.org; Thu, 01 Mar 2012 09:49:26 +0000 Received: by mail-ey0-f177.google.com with SMTP id k13so143864eaa.36 for ; Thu, 01 Mar 2012 01:49:25 -0800 (PST) Received-SPF: pass (google.com: domain of hechtb@googlemail.com designates 10.14.97.70 as permitted sender) client-ip=10.14.97.70; Authentication-Results: mr.google.com; spf=pass (google.com: domain of hechtb@googlemail.com designates 10.14.97.70 as permitted sender) smtp.mail=hechtb@googlemail.com; dkim=pass header.i=hechtb@googlemail.com Received: from mr.google.com ([10.14.97.70]) by 10.14.97.70 with SMTP id s46mr2631352eef.59.1330595365823 (num_hops = 1); Thu, 01 Mar 2012 01:49:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=epW5PAKufYQgJJofq+CMXvTcfwvgttEEs1YpvQ0Deos=; b=X+IEBKzQAPhQhPyL6rTmXG3sDO5uLnw0PwpLHXBG71ErLP9VFHGdw73WlXKkIEPYvm wXimqxYaChNGc2VfOydGU5T3du/dCJuQ1bVrJ745LuDBnZab80PkoXRw9Q7uIYp+Gk4/ xRU0E+zazoptW0BK0vwKJApdDhf5XTcjH3pdc= Received: by 10.14.97.70 with SMTP id s46mr2024579eef.59.1330595365741; Thu, 01 Mar 2012 01:49:25 -0800 (PST) Received: from localhost.localdomain ([89.204.153.40]) by mx.google.com with ESMTPS id n17sm5432919eei.3.2012.03.01.01.49.24 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 01 Mar 2012 01:49:25 -0800 (PST) From: Bastian Hecht To: linux-sh@vger.kernel.org, linux-mtd@lists.infradead.org Subject: [PATCH v3 5/7] mtd: sh_flctl: Use cached register value for FLCMNCR Date: Thu, 1 Mar 2012 10:48:39 +0100 Message-Id: <1330595321-2728-5-git-send-email-hechtb@gmail.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1330595321-2728-1-git-send-email-hechtb@gmail.com> References: <1330595321-2728-1-git-send-email-hechtb@gmail.com> X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.215.177 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (hechtb[at]googlemail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Magnus Damm , Laurent Pichart X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-mtd-bounces@lists.infradead.org Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Instead of reading out the register, use a cached value. This will make way for a proper runtime power management implementation. Signed-off-by: Bastian Hecht --- changelog: renamed flcmncr_val to flcmncr_base hwecc code needs to alter flcmncr_base too use cached value in set_cmd_regs too pull in the chip enable flag into the flcmncr_base value. I think it's easier to just modify flcmncr_base in flctl_select_chip() rather than adding another cached value for the enable flag. drivers/mtd/nand/sh_flctl.c | 22 +++++++--------------- include/linux/mtd/sh_flctl.h | 1 + 2 files changed, 8 insertions(+), 15 deletions(-) diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c index 5c3e71f..73398f7 100644 --- a/drivers/mtd/nand/sh_flctl.c +++ b/drivers/mtd/nand/sh_flctl.c @@ -283,7 +283,7 @@ static void write_fiforeg(struct sh_flctl *flctl, int rlen, int offset) static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_val) { struct sh_flctl *flctl = mtd_to_flctl(mtd); - uint32_t flcmncr_val = readl(FLCMNCR(flctl)) & ~SEL_16BIT; + uint32_t flcmncr_val = flctl->flcmncr_base & ~SEL_16BIT; uint32_t flcmdcr_val, addr_len_bytes = 0; /* Set SNAND bit if page size is 2048byte */ @@ -681,16 +681,15 @@ read_normal_exit: static void flctl_select_chip(struct mtd_info *mtd, int chipnr) { struct sh_flctl *flctl = mtd_to_flctl(mtd); - uint32_t flcmncr_val = readl(FLCMNCR(flctl)); switch (chipnr) { case -1: - flcmncr_val &= ~CE0_ENABLE; - writel(flcmncr_val, FLCMNCR(flctl)); + flctl->flcmncr_base &= ~CE0_ENABLE; + writel(flctl->flcmncr_base, FLCMNCR(flctl)); break; case 0: - flcmncr_val |= CE0_ENABLE; - writel(flcmncr_val, FLCMNCR(flctl)); + flctl->flcmncr_base |= CE0_ENABLE; + writel(flctl->flcmncr_base, FLCMNCR(flctl)); break; default: BUG(); @@ -748,11 +747,6 @@ static int flctl_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) return 0; } -static void flctl_register_init(struct sh_flctl *flctl, unsigned long val) -{ - writel(val, FLCMNCR(flctl)); -} - static int flctl_chip_init_tail(struct mtd_info *mtd) { struct sh_flctl *flctl = mtd_to_flctl(mtd); @@ -804,8 +798,7 @@ static int flctl_chip_init_tail(struct mtd_info *mtd) chip->ecc.mode = NAND_ECC_HW; /* 4 symbols ECC enabled */ - writel(readl(FLCMNCR(flctl)) | _4ECCEN | ECCPOS2 | ECCPOS_02, - FLCMNCR(flctl)); + flctl->flcmncr_base |= _4ECCEN | ECCPOS2 | ECCPOS_02; } else { chip->ecc.mode = NAND_ECC_SOFT; } @@ -851,10 +844,9 @@ static int __devinit flctl_probe(struct platform_device *pdev) nand = &flctl->chip; flctl_mtd->priv = nand; flctl->pdev = pdev; + flctl->flcmncr_base = pdata->flcmncr_val; flctl->hwecc = pdata->has_hwecc; - flctl_register_init(flctl, pdata->flcmncr_val); - nand->options = NAND_NO_AUTOINCR; /* Set address of hardware control function */ diff --git a/include/linux/mtd/sh_flctl.h b/include/linux/mtd/sh_flctl.h index b669405..c708282 100644 --- a/include/linux/mtd/sh_flctl.h +++ b/include/linux/mtd/sh_flctl.h @@ -132,6 +132,7 @@ struct sh_flctl { int erase1_page_addr; /* page_addr in ERASE1 cmd */ uint32_t erase_ADRCNT; /* bits of FLCMDCR in ERASE1 cmd */ uint32_t rw_ADRCNT; /* bits of FLCMDCR in READ WRITE cmd */ + uint32_t flcmncr_base; /* base value of FLCMNCR */ int hwecc_cant_correct[4];