From patchwork Tue Jun 28 11:50:56 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Ferre X-Patchwork-Id: 102350 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 73F8CB6F5F for ; Tue, 28 Jun 2011 20:43:54 +1000 (EST) Received: from canuck.infradead.org ([134.117.69.58]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QbVlf-0008FN-C9; Tue, 28 Jun 2011 10:43:43 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QbVle-0006eL-Vn; Tue, 28 Jun 2011 10:43:43 +0000 Received: from newsmtp5.atmel.com ([204.2.163.5] helo=sjogate2.atmel.com) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QbVlb-0006dz-Tx; Tue, 28 Jun 2011 10:43:40 +0000 Received: from meyreuil.atmel.fr ([10.159.254.132]) by sjogate2.atmel.com (8.13.6/8.13.6) with ESMTP id p5SAeVTO026745; Tue, 28 Jun 2011 03:40:32 -0700 (PDT) Received: from bendor.rfo.atmel.com ([10.159.245.201]) by meyreuil.atmel.fr (8.11.7p1+Sun/8.11.7) with ESMTP id p5SAhYa02939; Tue, 28 Jun 2011 12:43:35 +0200 (MEST) From: Nicolas Ferre To: linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH] MTD: atmel_nand: optimize read/write buffer functions Date: Tue, 28 Jun 2011 13:50:56 +0200 Message-Id: <1309261856-27402-1-git-send-email-nicolas.ferre@atmel.com> X-Mailer: git-send-email 1.7.3 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110628_064340_205353_76E0B2D8 X-CRM114-Status: GOOD ( 12.20 ) X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain Cc: hong.xu@atmel.com, Nicolas Ferre , linux-kernel@vger.kernel.org X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-mtd-bounces@lists.infradead.org Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org For PIO NAND access functions, we use the features of the SMC: - no need to take into account the NAND bus width: SMC will deal with this - a word aligned memcpy on the NAND chip-select space is able to generate proper SMC behavior while optimizing AHB bus usage thanks to optimized memcpy implementation. Signed-off-by: Nicolas Ferre --- drivers/mtd/nand/atmel_nand.c | 71 +++++++++++++++++----------------------- 1 files changed, 30 insertions(+), 41 deletions(-) diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index b300705..cb8a04b 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -160,37 +160,6 @@ static int atmel_nand_device_ready(struct mtd_info *mtd) !!host->board->rdy_pin_active_low; } -/* - * Minimal-overhead PIO for data access. - */ -static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len) -{ - struct nand_chip *nand_chip = mtd->priv; - - __raw_readsb(nand_chip->IO_ADDR_R, buf, len); -} - -static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len) -{ - struct nand_chip *nand_chip = mtd->priv; - - __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2); -} - -static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len) -{ - struct nand_chip *nand_chip = mtd->priv; - - __raw_writesb(nand_chip->IO_ADDR_W, buf, len); -} - -static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len) -{ - struct nand_chip *nand_chip = mtd->priv; - - __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2); -} - static void dma_complete_func(void *completion) { complete(completion); @@ -265,33 +234,53 @@ err_buf: static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len) { struct nand_chip *chip = mtd->priv; - struct atmel_nand_host *host = chip->priv; + u32 align; + u8 *pbuf; if (use_dma && len > mtd->oobsize) /* only use DMA for bigger than oob size: better performances */ if (atmel_nand_dma_op(mtd, buf, len, 1) == 0) return; - if (host->board->bus_width_16) - atmel_read_buf16(mtd, buf, len); - else - atmel_read_buf8(mtd, buf, len); + /* if no DMA operation possible, use PIO */ + pbuf = buf; + align = 0x03 & ((unsigned)pbuf); + + if (align) { + u32 align_len = 4 - align; + + /* non aligned buffer: re-align to next word boundary */ + ioread8_rep(chip->IO_ADDR_R, pbuf, align_len); + pbuf += align_len; + len -= align_len; + } + memcpy((void *)pbuf, chip->IO_ADDR_R, len); } static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len) { struct nand_chip *chip = mtd->priv; - struct atmel_nand_host *host = chip->priv; + u32 align; + const u8 *pbuf; if (use_dma && len > mtd->oobsize) /* only use DMA for bigger than oob size: better performances */ if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0) return; - if (host->board->bus_width_16) - atmel_write_buf16(mtd, buf, len); - else - atmel_write_buf8(mtd, buf, len); + /* if no DMA operation possible, use PIO */ + pbuf = buf; + align = 0x03 & ((unsigned)pbuf); + + if (align) { + u32 align_len = 4 - align; + + /* non aligned buffer: re-align to next word boundary */ + iowrite8_rep(chip->IO_ADDR_W, pbuf, align_len); + pbuf += align_len; + len -= align_len; + } + memcpy(chip->IO_ADDR_W, (void *)pbuf, len); } /*