From patchwork Mon Aug 16 08:09:09 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Axel Lin X-Patchwork-Id: 61785 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [18.85.46.34]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id DA337B6F11 for ; Mon, 16 Aug 2010 18:08:24 +1000 (EST) Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.72 #1 (Red Hat Linux)) id 1Okuif-0008TV-F4; Mon, 16 Aug 2010 08:06:57 +0000 Received: from mail-gw0-f49.google.com ([74.125.83.49]) by bombadil.infradead.org with esmtp (Exim 4.72 #1 (Red Hat Linux)) id 1OkuiW-0008SJ-Im for linux-mtd@lists.infradead.org; Mon, 16 Aug 2010 08:06:54 +0000 Received: by gwb10 with SMTP id 10so2195910gwb.36 for ; Mon, 16 Aug 2010 01:06:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:cc :content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=HeiwKHOle4osItAmH6DsOipOfYanZRc3k4o2IXQdCmQ=; b=YmWasijSl8eNShMDmToS3rxVn5tNBigk3XrIhUzmemy7tuqfh/YCneyQZVx0c7PjPb k+wdSRYAfbBnqSnMBQoNDHVgnEsH5yc5rAkOnU4b47JtXF7XONSuAKTTGciYpyAaVtqD 6xFKLxoRikFcsW8l+uB9SRwPeiYmgVMOcHeMs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; b=oZci4J39vq5NO8pQdljuH0rEzpJkY7T9XaVAAGAYhvkLGxjCWr3rK+xuOSE/6wPG04 fF28QO/Uy75y5vx0tx7DxchFxCDx5oPA0yxx7HsU4zxH/NtcsYS7Fo8PCWWvoJuaIeow OhI9L/L71Do5TkxvQUZJyB9AAb9opVCMo3FGM= Received: by 10.100.171.16 with SMTP id t16mr5353818ane.83.1281946006483; Mon, 16 Aug 2010 01:06:46 -0700 (PDT) Received: from [192.168.100.50] (60-251-136-127.HINET-IP.hinet.net [60.251.136.127]) by mx.google.com with ESMTPS id b17sm9934050anh.5.2010.08.16.01.06.43 (version=SSLv3 cipher=RC4-MD5); Mon, 16 Aug 2010 01:06:45 -0700 (PDT) Subject: [PATCH] [MTD] [NAND] pxa3xx: fix ns2cycle equation From: Axel Lin To: linux-kernel Date: Mon, 16 Aug 2010 16:09:09 +0800 Message-Id: <1281946149.10299.1.camel@mola> Mime-Version: 1.0 X-Mailer: Evolution 2.22.3.1 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20100816_040648_763814_A47D2313 X-CRM114-Status: GOOD ( 16.14 ) X-Spam-Score: -0.1 (/) X-Spam-Report: SpamAssassin version 3.3.1 on bombadil.infradead.org summary: Content analysis details: (-0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is freemail (axel.lin[at]gmail.com) -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, low trust [74.125.83.49 listed in list.dnswl.org] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Eric Miao , Matt Reimer , David Woodhouse , linux-mtd@lists.infradead.org X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-mtd-bounces@lists.infradead.org Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Test on a PXA310 platform with Samsung K9F2G08X0B NAND flash, with tCH=5 and clk is 156MHz, ns2cycle(5, 156000000) returns -1. ns2cycle returns negtive value will break NDTR0_tXX macros. After checking the commit log, I found the problem is introduced by commit 5b0d4d7c8a67c5ba3d35e6ceb0c5530cc6846db7 "[MTD] [NAND] pxa3xx: convert from ns to clock ticks more accurately" To get num of clock cycles, we use below equation: num of clock cycles = time (ns) / one clock cycle (ns) + 1 We need to add 1 cycle here because integer division will truncate the result. It is possible the developers set the Min values in SPEC for timing settings. Thus the truncate may cause problem, and it is safe to add an extra cycle here. The various fields in NDTR{01} are in units of clock ticks minus one, thus we should subtract 1 cycle then. Thus the correct equation should be: num of clock cycles = time (ns) / one clock cycle (ns) + 1 - 1 = time (ns) / one clock cycle (ns) Signed-off-by: Axel Lin Acked-by: Eric Miao --- drivers/mtd/nand/pxa3xx_nand.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index e02fa4f..4d89f37 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -363,7 +363,7 @@ static struct pxa3xx_nand_flash *builtin_flash_types[] = { #define tAR_NDTR1(r) (((r) >> 0) & 0xf) /* convert nano-seconds to nand flash controller clock cycles */ -#define ns2cycle(ns, clk) (int)(((ns) * (clk / 1000000) / 1000) - 1) +#define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000) /* convert nand flash controller clock cycles to nano-seconds */ #define cycle2ns(c, clk) ((((c) + 1) * 1000000 + clk / 500) / (clk / 1000))