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([79.115.63.75]) by smtp.gmail.com with ESMTPSA id lv23-20020a170906bc9700b009f28db2b702sm3390163ejb.209.2023.11.25.04.35.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 04:35:40 -0800 (PST) From: Tudor Ambarus To: pratyush@kernel.org, michael@walle.cc, fastevam@denx.de Cc: linux-mtd@lists.infradead.org, takahiro.kuwano@infineon.com, bacem.daassi@infineon.com, linux-kernel@vger.kernel.org, Tudor Ambarus Subject: [PATCH v3 0/5] mtd: spi-nor: introduce die erase Date: Sat, 25 Nov 2023 14:35:24 +0200 Message-Id: <20231125123529.55686-1-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1993; i=tudor.ambarus@linaro.org; h=from:subject; bh=ET4nej2fkYuJJH06/u65/dyHT3qeYqBPblhk2M6LCWI=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBlYeoQsHuuLgw++eZrR2gX5lRXMpqhMPjGC7Axs 3i2O3dC7DyJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZWHqEAAKCRBLVU9HpY0U 6b10B/9kyec2DqmHLyLcwnNX34fGbimfAQ4jI5UXnDPE/nJg9rxb1rcFQn9OicZcLu+Ti+Ps4H7 kOVjCp9aN48lmDbFgysb71OH1VZb482V8LBOalMJ1wgWL8uI+o4xhd1iL6yF93QEIsEdc7KYyKD K+6A4x6DilnL2afQqE3vaW76C+gvgXrAHnBmV25bV65tVZ0a5u/6tUsDMKRpxUO+HypG3Y6rp2h JGXx/8mY8M+BDcJi3j280BIDLN9C40cUstjP7dhku1QqiP0FPRxjlPI3HMjgtdfl6B8zdfR68iR 6w2xhY7lh+UezCV69t0HbURKKmPmIIM8S/tiB0kSCFAJZlFH X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231125_043545_065244_2EF65D7B X-CRM114-Status: GOOD ( 13.15 ) X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: changes in v3: - fix code, thanks to Fabio's testing - found a n25q00 and tested on my side too - fixed micron's die erase support Add support for die erase. JESD216 mentions die erase, but does not provide an opcode for it. Check BFPT dword 11, bits 30:24, "Chip Erase, Typical time", it says: Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:234 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org changes in v3: - fix code, thanks to Fabio's testing - found a n25q00 and tested on my side too - fixed micron's die erase support Add support for die erase. JESD216 mentions die erase, but does not provide an opcode for it. Check BFPT dword 11, bits 30:24, "Chip Erase, Typical time", it says: "Typical time to erase one chip (die). User must poll device busy to determine if the operation has completed. For a device consisting of multiple dies, that are individually accessed, the time is for each die to which a chip erase command is applied." So when a flash consists of a single die, this is the erase time for the full chip (die) erase, and when it consists of multiple dies, it's the die erase time. Chip and die are the same thing. For what concerns the Micron flashes, unfortunately Micron does not provide a 4-byte opcode equivalent for the die erase. The SFDP 4BAIT table fails to consider the die erase too, the standard can be improved. Thus we're forced to enter in the 4 byte address mode in order to benefit of the die erase. This comes with some changes into the core. Tested on n25q00. This flash defines the 4BAIT SFDP table, thus it will use the 4BAIT opcodes for reads, page programs or erases, with the exception that it will use the die erase command in the 4 byte address mode. Fabio Estevam (1): mtd: spi-nor: micron-st: Add support for mt25qu01g Tudor Ambarus (4): mtd: spi-nor: add erase die (chip) capability mtd: spi-nor: spansion: enable die erase for multi die flashes mtd: spi-nor: micron-st: enable die erase for multi die flashes mtd: spi-nor: remove NO_CHIP_ERASE flag drivers/mtd/spi-nor/core.c | 143 ++++++++++++++++++++------------ drivers/mtd/spi-nor/core.h | 16 ++-- drivers/mtd/spi-nor/debugfs.c | 2 +- drivers/mtd/spi-nor/micron-st.c | 59 ++++++++++++- drivers/mtd/spi-nor/spansion.c | 4 +- 5 files changed, 158 insertions(+), 66 deletions(-) Tested-by: Fabio Estevam