mbox series

[v2,0/4] STIG Mode Fixes for spi-cadence-qspi driver

Message ID 20230125081023.1573712-1-d-gole@ti.com
Headers show
Series STIG Mode Fixes for spi-cadence-qspi driver | expand

Message

Dhruva Gole Jan. 25, 2023, 8:10 a.m. UTC 
* Reset the CMD_CTRL Register, without which read/writes in STIG mode
were failing in some cases. The issue came to light while using STIG
Mode for small reads.
* Also add a flag that can allow us to do direct reads but distinguish
direct writes, thus enabling us to disable writes in DAC mode in some
cases that require it. (Like to write to some connected Flash registers)
* Fix register reads in STIG mode and also use STIG mode while reading flash
registers.
Currently if you try to read a register while in STIG mode there is no
support for ADDR and thus naturally a register never gets read from the
flash.

This patch series has been tested on a TI AM625-SK-EVM with both a quad
spi nor flash (s25hs) and OSPI NOR Flash (s28hs).

Output of ltp-ddt test, "DD_RW_ERASESIZE_UBIFS" run with s25hs512t flash:
...
[    2.334068] spi-nor spi0.0: s25hs512t (65536 Kbytes)
[    2.339185] 7 fixed-partitions partitions found on MTD device
fc40000.spi.0
[    2.346158] Creating 7 MTD partitions on "fc40000.spi.0":
[    2.351555] 0x000000000000-0x000000080000 : "ospi.tiboot3"
[    2.358344] 0x000000080000-0x000000280000 : "ospi.tispl"
[    2.364788] 0x000000280000-0x000000680000 : "ospi.u-boot"
[    2.371311] 0x000000680000-0x0000006c0000 : "ospi.env"
[    2.377519] 0x0000006c0000-0x000000700000 : "ospi.env.backup"
[    2.384419] 0x000000800000-0x000003fc0000 : "ospi.rootfs"
[    2.390890] 0x000003fc0000-0x000004000000 : "ospi.phypattern"
..snip..
Test Start Time: Wed Jan 11 21:14:31 2023
-----------------------------------------
Testcase                                           Result     Exit Value
--------                                           ------     ----------
OSPI_S_FUNC_DD_RW_ERASESIZE_UBIFS                  PASS       0

-----------------------------------------------
Total Tests: 1
Total Skipped Tests: 0
Total Failures: 0
Kernel Version: 6.2.0-rc1-00040-g700d796a94e0-dirty
Machine Architecture: aarch64
Hostname: am62xx-evm
...

Previous version link:
https://lore.kernel.org/linux-spi/20230104062604.1556763-1-d-gole@ti.com/

Changelog:

* This version addresses concerns from Vaishnav where he was seeing issues
while testing on different platforms.
* Also has additional patches that fix the issues that came to light
while using STIG Mode.

To: Mark Brown <broonie@kernel.org>
Cc: Vaishnav Achath <vaishnav.a@ti.com>
Cc: Pratyush Yadav <pratyush@kernel.org>
Cc: Vignesh Raghavendra <vigneshr@ti.com>

Dhruva Gole (4):
  spi: cadence-quadspi: Reset CMD_CTRL Reg on cmd r/w completion
  spi: cadence-quadspi: Add flag for direct mode writes
  spi: cadence-quadspi: setup ADDR Bits in cmd reads
  spi: cadence-quadspi: use STIG mode for small reads

 drivers/spi/spi-cadence-quadspi.c | 42 ++++++++++++++++++++++++++++---
 1 file changed, 38 insertions(+), 4 deletions(-)

--
2.25.1

Comments

Mark Brown Feb. 14, 2023, 9:10 p.m. UTC | #1 
On Wed, 25 Jan 2023 13:40:19 +0530, Dhruva Gole wrote:
> * Reset the CMD_CTRL Register, without which read/writes in STIG mode
> were failing in some cases. The issue came to light while using STIG
> Mode for small reads.
> * Also add a flag that can allow us to do direct reads but distinguish
> direct writes, thus enabling us to disable writes in DAC mode in some
> cases that require it. (Like to write to some connected Flash registers)
> * Fix register reads in STIG mode and also use STIG mode while reading flash
> registers.
> Currently if you try to read a register while in STIG mode there is no
> support for ADDR and thus naturally a register never gets read from the
> flash.
> 
> [...]

Applied to

   broonie/spi.git for-next

Thanks!

[1/4] spi: cadence-quadspi: Reset CMD_CTRL Reg on cmd r/w completion
      commit: d4f43a2d05faf7febb839edb2e9e8f85dfb9d2d2
[2/4] spi: cadence-quadspi: Add flag for direct mode writes
      commit: e8c51b164355c1d519a4b8ad0873f131035d26b7
[3/4] spi: cadence-quadspi: setup ADDR Bits in cmd reads
      commit: a8674ae02db232927385c2d0a063e10c0118f5ca
[4/4] spi: cadence-quadspi: use STIG mode for small reads
      commit: d403fb6e76bf854ef0f7d84e797e51b9494788e0

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark