Message ID | cover.1549623801.git.horms+renesas@verge.net.au |
---|---|
State | New |
Headers | show |
Series | [GIT,PULL] Second Round of Renesas ARM64 Based SoC DT Updates for v5.1 | expand |
Hello! On 02/08/2019 02:13 PM, Simon Horman wrote: > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > > This patch defines OOP tables for all CPUs, similarly to > what done by Takeshi Kihara and Yoshihiro Kaneko for the > R8A77990. > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au> [...] > @@ -55,6 +76,8 @@ > power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; > next-level-cache = <&L2_CA53>; > enable-method = "psci"; > + clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>; Need space after =... > + operating-points-v2 = <&cluster1_opp>; > }; > > a53_1: cpu@1 { > @@ -64,6 +87,8 @@ > power-domains = <&sysc R8A774C0_PD_CA53_CPU1>; > next-level-cache = <&L2_CA53>; > enable-method = "psci"; > + clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>; Here as well... > + operating-points-v2 = <&cluster1_opp>; > }; > > L2_CA53: cache-controller-0 { MBR, Sergei
Hello Sergei, Thank you for your feedback! > -----Original Message----- > From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > Sent: 08 February 2019 12:53 > To: Simon Horman <horms+renesas@verge.net.au>; linux-renesas-soc@vger.kernel.org > Cc: linux-arm-kernel@lists.infradead.org; Magnus Damm <magnus.damm@gmail.com>; Fabrizio Castro > <fabrizio.castro@bp.renesas.com> > Subject: Re: [PATCH 08/12] arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices > > Hello! > > On 02/08/2019 02:13 PM, Simon Horman wrote: > > > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > > > > This patch defines OOP tables for all CPUs, similarly to > > what done by Takeshi Kihara and Yoshihiro Kaneko for the > > R8A77990. > > > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au> > [...] > > @@ -55,6 +76,8 @@ > > power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; > > next-level-cache = <&L2_CA53>; > > enable-method = "psci"; > > +clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>; > > Need space after =... Doh! Simon, do you want me to send another version to fix both spacing issues? Thanks, Fab > > > +operating-points-v2 = <&cluster1_opp>; > > }; > > > > a53_1: cpu@1 { > > @@ -64,6 +87,8 @@ > > power-domains = <&sysc R8A774C0_PD_CA53_CPU1>; > > next-level-cache = <&L2_CA53>; > > enable-method = "psci"; > > +clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>; > > > Here as well... > > > +operating-points-v2 = <&cluster1_opp>; > > }; > > > > L2_CA53: cache-controller-0 { > > MBR, Sergei Renesas Electronics Europe GmbH,Geschaeftsfuehrer/President : Michael Hannawald, Sitz der Gesellschaft/Registered office: Duesseldorf, Arcadiastrasse 10, 40472 Duesseldorf, Germany,Handelsregister/Commercial Register: Duesseldorf, HRB 3708 USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE reg. no.: DE 14978647
On Fri, Feb 08, 2019 at 03:26:49PM +0000, Fabrizio Castro wrote: > Hello Sergei, > > Thank you for your feedback! > > > -----Original Message----- > > From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > > Sent: 08 February 2019 12:53 > > To: Simon Horman <horms+renesas@verge.net.au>; linux-renesas-soc@vger.kernel.org > > Cc: linux-arm-kernel@lists.infradead.org; Magnus Damm <magnus.damm@gmail.com>; Fabrizio Castro > > <fabrizio.castro@bp.renesas.com> > > Subject: Re: [PATCH 08/12] arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices > > > > Hello! > > > > On 02/08/2019 02:13 PM, Simon Horman wrote: > > > > > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > > > > > > This patch defines OOP tables for all CPUs, similarly to > > > what done by Takeshi Kihara and Yoshihiro Kaneko for the > > > R8A77990. > > > > > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au> > > [...] > > > @@ -55,6 +76,8 @@ > > > power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; > > > next-level-cache = <&L2_CA53>; > > > enable-method = "psci"; > > > +clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>; > > > > Need space after =... > > Doh! Simon, do you want me to send another version to fix both spacing issues? Likewise, sorry I didn't notice that earlier. I'd rather not re-send this pull request just to resolve whitespace issues. So please send an incremental patch for now.
Hello Simon, > From: Simon Horman <horms@verge.net.au> > Sent: 11 February 2019 09:50 > Subject: Re: [PATCH 08/12] arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices > > On Fri, Feb 08, 2019 at 03:26:49PM +0000, Fabrizio Castro wrote: > > Hello Sergei, > > > > Thank you for your feedback! > > > > > -----Original Message----- > > > From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > > > Sent: 08 February 2019 12:53 > > > To: Simon Horman <horms+renesas@verge.net.au>; linux-renesas-soc@vger.kernel.org > > > Cc: linux-arm-kernel@lists.infradead.org; Magnus Damm <magnus.damm@gmail.com>; Fabrizio Castro > > > <fabrizio.castro@bp.renesas.com> > > > Subject: Re: [PATCH 08/12] arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices > > > > > > Hello! > > > > > > On 02/08/2019 02:13 PM, Simon Horman wrote: > > > > > > > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > > > > > > > > This patch defines OOP tables for all CPUs, similarly to > > > > what done by Takeshi Kihara and Yoshihiro Kaneko for the > > > > R8A77990. > > > > > > > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > > > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au> > > > [...] > > > > @@ -55,6 +76,8 @@ > > > > power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; > > > > next-level-cache = <&L2_CA53>; > > > > enable-method = "psci"; > > > > +clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>; > > > > > > Need space after =... > > > > Doh! Simon, do you want me to send another version to fix both spacing issues? > > Likewise, sorry I didn't notice that earlier. > > I'd rather not re-send this pull request just to resolve whitespace issues. > So please send an incremental patch for now. Thanks, will do. Cheers, Fab Renesas Electronics Europe GmbH,Geschaeftsfuehrer/President : Michael Hannawald, Sitz der Gesellschaft/Registered office: Duesseldorf, Arcadiastrasse 10, 40472 Duesseldorf, Germany,Handelsregister/Commercial Register: Duesseldorf, HRB 3708 USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE reg. no.: DE 14978647
On Fri, Feb 8, 2019 at 12:13 PM Simon Horman <horms+renesas@verge.net.au> wrote: > Second Round of Renesas ARM64 Based SoC DT Updates for v5.1 > > * R-Car Gen3 SoC based Salvator-X, Salvator-XS and ULCB boards > - Enable HS400 support for eMMC > > * R-Car E3 (r7a77990) SoC > - Add OPPs table for cpu devices > > * RZ/G2E (r8a774c0) SoC > - Describe TMU, CMT, SDHI devices in DT > - Describe pincontrol support for SCIF2 device in DT > - Add OPPs table for cpu devices > > * RZ/G2E (r8a774c0) based EK874 board and CAT875 sub-board, > and CAT874 board > - Initial support Pulled into arm/dt, thanks! Arnd