From patchwork Tue Feb 11 19:33:11 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jasbir Matharu X-Patchwork-Id: 319391 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from casper.infradead.org (unknown [IPv6:2001:770:15f::2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 6EFEC2C009B for ; Wed, 12 Feb 2014 06:39:04 +1100 (EST) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WDJAF-0003lU-FL; Tue, 11 Feb 2014 19:38:39 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WDJ5N-0008Rb-Lc; Tue, 11 Feb 2014 19:33:37 +0000 Received: from mail-wi0-x244.google.com ([2a00:1450:400c:c05::244]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WDJ5K-0008Qg-Ug for linux-arm-kernel@lists.infradead.org; Tue, 11 Feb 2014 19:33:35 +0000 Received: by mail-wi0-f196.google.com with SMTP id hm4so1595664wib.3 for ; Tue, 11 Feb 2014 11:33:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:date:message-id:subject:from:to:content-type; bh=bkWIiFpUaHqmuXCrhR3fLZ7whKNm5wdMKAe/2m6RauE=; b=xLdJuIQBrR+Gs6ASOUPVxtKxHsBBUD6nR4iQvXqjVXB/eYsHSdS1cpnkgwq2v7uL31 RytfUUnGHgaDadzYu1cR5gx/0IKQYKKhCmLMoeDQIr+qjkdaD7DmZ8GAoHQZHFt0rvxZ vLg9TJTH5CkjcX7SIuawLDIUi+JpsLpaNC1hTSz59I619liWFnAHeeyIKzaSZ/vyXrIR 8PWyNAHj8T1au9utRG9PhduRuhyoTZbD/MWBqQReL2Spf4kjv5dCz1R/rqz5+kF5w+hU 9amFM/ZaFcxVwCv2Ff9fXko33g6dSL6s6doTPuqcyowBYzTbt6hAZvfKHeA8HNVVxm24 rJzQ== MIME-Version: 1.0 X-Received: by 10.194.186.204 with SMTP id fm12mr27753388wjc.27.1392147191559; Tue, 11 Feb 2014 11:33:11 -0800 (PST) Received: by 10.194.157.165 with HTTP; Tue, 11 Feb 2014 11:33:11 -0800 (PST) Date: Tue, 11 Feb 2014 19:33:11 +0000 Message-ID: Subject: Toggling gpio pins while powering down From: Jasbir Matharu To: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140211_143335_110076_D8864FFE X-CRM114-Status: GOOD ( 13.19 ) X-Spam-Score: -1.8 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.8 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (jasbirm66[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit (jasbirm66[at]gmail.com) -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org I'm trying to determine the correct way of toggling gpio pins when the soc is powering down to enter low power mode. My current crude implementation is perform these within a pm_power_off function however this is currently done within the board file by checking for a compatible board type (ugly). The alternative would be create a driver and implement the pm_power_off function within. However given there could many drivers implementing a pm_power_off functions there's no guarantee mine will be called? Another requirement is that the gpio need to be set in the correct order. struct device *parent; @@ -353,6 +403,8 @@ static void __init imx6q_init_machine(void) imx6_pm_init(); imx6q_csi_mux_init(); imx6q_lvds_cabc_init(); + + pm_power_off = imx6q_poweroff; } diff --git a/arch/arm/boot/dts/imx6q-udoo.dts b/arch/arm/boot/dts/imx6q-udoo.dts index 0ce92cd..e5e2af9 100644 --- a/arch/arm/boot/dts/imx6q-udoo.dts +++ b/arch/arm/boot/dts/imx6q-udoo.dts @@ -62,6 +62,13 @@ compatible = "fsl,mxc_v4l2_output"; status = "okay"; }; + + poweroff { + compatible = "udoo,poweroff"; + sam3x_rst_gpio = <&gpio1 0 0>; + pwr_5v_gpio = <&gpio2 4 0>; + }; + }; &hdmi_audio { diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index f24c231..3fea3fd 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include @@ -336,6 +337,55 @@ static const struct of_dev_auxdata imx6q_auxdata_lookup[] __initconst = { { /* sentinel */ } }; +#define SNVS_LPCR 0x04 +static void imx6q_poweroff(void) +{ + struct device_node *snvs_np, *pwr_off_np; + void __iomem *mx6_snvs_base; + u32 value; + int sam3x_rst_gpio,pwr_5v_gpio; + + snvs_np = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0-mon-rtc-lp"); + if (!snvs_np) { + pr_warn("failed to find sec-v4.0-mon-rtc-lp node\n"); + return; + } + + mx6_snvs_base = of_iomap(snvs_np, 0); + if (!mx6_snvs_base) { + pr_warn("failed to map sec-v4.0-mon-rtc-lp\n"); + goto put_snvs_node; + } + + value = readl(mx6_snvs_base + SNVS_LPCR); + /*set TOP and DP_EN bit*/ + writel(value | 0x60, mx6_snvs_base + SNVS_LPCR); + + if (of_machine_is_compatible("udoo,imx6q-udoo")) { + // Power down SAM3X and UDOO + pwr_off_np = of_find_compatible_node(NULL, NULL, "udoo,poweroff"); + if (!pwr_off_np) { + pr_warn("failed to find udoo,poweroff node\n"); + goto put_snvs_node; + } + + sam3x_rst_gpio = of_get_named_gpio(pwr_off_np, "sam3x_rst_gpio", 0); + pwr_5v_gpio = of_get_named_gpio(pwr_off_np, "pwr_5v_gpio", 0); + if (gpio_is_valid(sam3x_rst_gpio) && gpio_is_valid(pwr_5v_gpio)) { + gpio_request_one(sam3x_rst_gpio, GPIOF_OUT_INIT_LOW,"sam3x_rst_gpio"), + msleep(5); + gpio_request_one(pwr_5v_gpio, GPIOF_OUT_INIT_HIGH,"pwr_5v_gpio"); + } else { + pr_warn("failed to find sam3x_rst_gpio or pwr_5v_gpio property\n"); + } + + } + + of_node_put(pwr_off_np); +put_snvs_node: + of_node_put(snvs_np); +} + static void __init imx6q_init_machine(void) {