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[178.255.168.35]) by smtp.gmail.com with ESMTPSA id m23sm2472105wrm.73.2017.08.04.03.29.56 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Fri, 04 Aug 2017 03:29:57 -0700 (PDT) From: Michal Simek To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/2] ARM: zynq: Add support for Zynq-7000S devices Date: Fri, 4 Aug 2017 12:29:54 +0200 Message-Id: <84fc91f48dffbd68aa569f482a178dc9c1703339.1501842586.git.michal.simek@xilinx.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <4b4bfaad88f16d7229bf3da58be8f50f9d82a461.1501842586.git.michal.simek@xilinx.com> References: <4b4bfaad88f16d7229bf3da58be8f50f9d82a461.1501842586.git.michal.simek@xilinx.com> In-Reply-To: <4b4bfaad88f16d7229bf3da58be8f50f9d82a461.1501842586.git.michal.simek@xilinx.com> References: <4b4bfaad88f16d7229bf3da58be8f50f9d82a461.1501842586.git.michal.simek@xilinx.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170804_033020_146505_502BB662 X-CRM114-Status: GOOD ( 19.66 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [2a00:1450:400c:c09:0:0:0:242 listed in] [list.dnswl.org] 0.0 HEADER_FROM_DIFFERENT_DOMAINS From and EnvelopeFrom 2nd level mail domains are different -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Peter Crosthwaite , Josh Cartwright , monstr@monstr.eu, linux-kernel@vger.kernel.org, Rob Herring , Rob Herring , Russell King , Steffen Trumtrar , =?UTF-8?q?S=C3=B6ren=20Brinkmann?= Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org Patch adds detection of Zynq-7000 base silicon configuration, namely Dual or Single CPU. Device trees attempting to enable DUAL CORE behavior on SINGLE CPU Zynq-7000S devices are prevented from corrupting system behavior. Detection of Dual or Single CPU is done via eFuses. Signed-off-by: Michal Simek Acked-by: Sören Brinkmann --- arch/arm/boot/dts/zynq-7000.dtsi | 5 +++ arch/arm/mach-zynq/Makefile | 2 +- arch/arm/mach-zynq/common.c | 1 + arch/arm/mach-zynq/common.h | 3 ++ arch/arm/mach-zynq/efuse.c | 75 ++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-zynq/platsmp.c | 3 ++ 6 files changed, 88 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-zynq/efuse.c diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index f3ac9bfe580e..ac37d46b2eab 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -305,6 +305,11 @@ syscon = <&slcr>; }; + efuse: efuse@f800d000 { + compatible = "xlnx,zynq-efuse"; + reg = <0xf800d000 0x20>; + }; + global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile index b03a97eb7501..1fc2d4b53a5e 100644 --- a/arch/arm/mach-zynq/Makefile +++ b/arch/arm/mach-zynq/Makefile @@ -3,5 +3,5 @@ # # Common support -obj-y := common.o slcr.o pm.o +obj-y := common.o efuse.o slcr.o pm.o obj-$(CONFIG_SMP) += headsmp.o platsmp.o diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index 6aba9ebf8041..5f28f7220d48 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -182,6 +182,7 @@ static void __init zynq_map_io(void) static void __init zynq_irq_init(void) { + zynq_early_efuse_init(); zynq_early_slcr_init(); irqchip_init(); } diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h index e771933db7e8..33742c3308e0 100644 --- a/arch/arm/mach-zynq/common.h +++ b/arch/arm/mach-zynq/common.h @@ -25,6 +25,9 @@ extern void zynq_slcr_cpu_state_write(int cpu, bool die); extern u32 zynq_slcr_get_device_id(void); +extern bool zynq_efuse_cpu_state(int cpu); +extern int zynq_early_efuse_init(void); + #ifdef CONFIG_SMP extern char zynq_secondary_trampoline; extern char zynq_secondary_trampoline_jump; diff --git a/arch/arm/mach-zynq/efuse.c b/arch/arm/mach-zynq/efuse.c new file mode 100644 index 000000000000..d31a5822ec65 --- /dev/null +++ b/arch/arm/mach-zynq/efuse.c @@ -0,0 +1,75 @@ +/* + * Xilinx EFUSE driver + * + * Copyright (c) 2016 Xilinx Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include "common.h" + +#define EFUSE_STATUS_OFFSET 0x10 + +/* 0 means cpu1 is working, 1 means cpu1 is broken */ +#define EFUSE_STATUS_CPU_BIT BIT(7) + +void __iomem *zynq_efuse_base; + +/** + * zynq_efuse_cpu_state - Read/write cpu state + * @cpu: cpu number + * + * Return: true if cpu is running, false if cpu is broken + */ +bool zynq_efuse_cpu_state(int cpu) +{ + u32 state; + + if (!cpu) + return true; + + state = readl(zynq_efuse_base + EFUSE_STATUS_OFFSET); + state &= EFUSE_STATUS_CPU_BIT; + + if (!state) + return true; + + return false; +} + +/** + * zynq_early_efuse_init - Early efuse init function + * + * Return: 0 on success, negative errno otherwise. + * + * Called very early during boot from platform code. + */ +int __init zynq_early_efuse_init(void) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-efuse"); + if (!np) { + pr_err("%s: no efuse node found\n", __func__); + BUG(); + } + + zynq_efuse_base = of_iomap(np, 0); + if (!zynq_efuse_base) { + pr_err("%s: Unable to map I/O memory\n", __func__); + BUG(); + } + + np->data = (__force void *)zynq_efuse_base; + + pr_info("%s mapped to %p\n", np->name, zynq_efuse_base); + + of_node_put(np); + + return 0; +} diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c index caa6d5fe9078..3d81e0f2972f 100644 --- a/arch/arm/mach-zynq/platsmp.c +++ b/arch/arm/mach-zynq/platsmp.c @@ -89,6 +89,9 @@ int zynq_cpun_start(u32 address, int cpu) static int zynq_boot_secondary(unsigned int cpu, struct task_struct *idle) { + if (!zynq_efuse_cpu_state(cpu)) + return -1; + return zynq_cpun_start(__pa_symbol(secondary_startup), cpu); }