From patchwork Wed Sep 10 07:43:41 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Anson.Huang@freescale.com" X-Patchwork-Id: 387597 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2001:1868:205::9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 696C0140170 for ; Wed, 10 Sep 2014 17:46:20 +1000 (EST) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XRcZU-0004lT-2y; Wed, 10 Sep 2014 07:44:08 +0000 Received: from mail-bl2on0106.outbound.protection.outlook.com ([65.55.169.106] helo=na01-bl2-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XRcZQ-0004Vn-Bp for linux-arm-kernel@lists.infradead.org; Wed, 10 Sep 2014 07:44:05 +0000 Received: from BN1PR0301MB0628.namprd03.prod.outlook.com (25.160.171.13) by BN1PR0301MB0626.namprd03.prod.outlook.com (25.160.171.11) with Microsoft SMTP Server (TLS) id 15.0.1024.12; Wed, 10 Sep 2014 07:43:41 +0000 Received: from BN1PR0301MB0628.namprd03.prod.outlook.com ([25.160.171.13]) by BN1PR0301MB0628.namprd03.prod.outlook.com ([25.160.171.13]) with mapi id 15.00.1019.015; Wed, 10 Sep 2014 07:43:41 +0000 From: "Anson.Huang@freescale.com" To: Shawn Guo Subject: RE: [PATCH V2 3/3] ARM: imx: source gpt per clk from OSC for system timer Thread-Topic: [PATCH V2 3/3] ARM: imx: source gpt per clk from OSC for system timer Thread-Index: AQHPyLnjfsB24dF+XUGri5+BqvVeEpvycxEAgAANqLaAB4DigIAAAI6A Date: Wed, 10 Sep 2014 07:43:41 +0000 Message-ID: <7fd82b8c08c54f4dadb6b7402231a086@BN1PR0301MB0628.namprd03.prod.outlook.com> References: <1409887606-22388-1-git-send-email-b20788@freescale.com> <1409887606-22388-4-git-send-email-b20788@freescale.com> <5E619FDB-56BB-486E-B627-9D2A9D4F9F54@freescale.com> <20140910073333.GC22579@dragon> In-Reply-To: <20140910073333.GC22579@dragon> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [123.151.195.49] x-microsoft-antispam: BCL:0;PCL:0;RULEID:;UriScan:; x-forefront-prvs: 033054F29A x-forefront-antispam-report: SFV:NSPM; SFS:(10019019)(6009001)(51704005)(189002)(13464003)(377424004)(199003)(24454002)(377454003)(74662001)(81342001)(74502001)(80022001)(31966008)(83072002)(4396001)(76576001)(64706001)(87936001)(99396002)(85852003)(101416001)(79102001)(97736003)(81542001)(74316001)(20776003)(108616004)(85306004)(93886004)(2656002)(21056001)(106116001)(50986999)(33646002)(99286002)(107046002)(95666004)(46102001)(83322001)(19580405001)(76482001)(19580395003)(90102001)(110136001)(106356001)(54356999)(105586002)(77982001)(86362001)(66066001)(76176999)(575784001)(92566001)(77096002)(24736002); DIR:OUT; SFP:1102; SCL:1; SRVR:BN1PR0301MB0626; H:BN1PR0301MB0628.namprd03.prod.outlook.com; FPR:; MLV:sfv; PTR:InfoNoRecords; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140910_004404_627751_466024FC X-CRM114-Status: GOOD ( 22.02 ) X-Spam-Score: -1.8 (-) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-1.8 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [65.55.169.106 listed in list.dnswl.org] -1.8 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [65.55.169.106 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record Cc: "devicetree@vger.kernel.org" , Fabio Estevam , "linux-arm-kernel@lists.infradead.org" , Sascha Hauer X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org Hi, Shawn Please see below response: Best regards! Anson Huang -----Original Message----- From: Shawn Guo [mailto:shawn.guo@linaro.org] Sent: 2014-09-10 3:34 PM To: Huang Yongcai-B20788 Cc: Fabio Estevam; Sascha Hauer; devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH V2 3/3] ARM: imx: source gpt per clk from OSC for system timer On Fri, Sep 05, 2014 at 12:58:28PM +0000, Anson.Huang@freescale.com wrote: > >> @@ -312,10 +318,26 @@ static void __init _mxc_timer_init(int irq, > >> __raw_writel(0, timer_base + MXC_TCTL); > >> __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet > >> note */ > >> > >> - if (timer_is_v2()) > >> - tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; > >> - else > >> + if (timer_is_v2()) { > >> + if (((cpu_is_imx6q() && imx_get_soc_revision() > > >> + IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl() || > >> + cpu_is_imx6sx()) && (clk_get_rate(clk_per) == > >> + V2_TIMER_RATE_OSC_DIV8)) { > >> + tctl_val = V2_TCTL_CLK_OSC_DIV8 | V2_TCTL_FRR | > >> + V2_TCTL_WAITEN | MXC_TCTL_TEN; > >> + if (cpu_is_imx6dl() || cpu_is_imx6sx()) { > >> + /* 24 / 8 = 3 MHz */ > >> + tprer_val = 7 << V2_TPRER_PRE24M; > >> + __raw_writel(tprer_val, timer_base + MXC_TPRER); > >> + tctl_val |= V2_TCTL_24MEN; > >> + } > >> + } else { > >> + tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | > >> + V2_TCTL_WAITEN | MXC_TCTL_TEN; > >> + } > >> + } else { > >> tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | > >> MXC_TCTL_TEN; > >> + } > > > > Can this block be rearranged a bit so that it becomes easier to read? > > I have to consider v1, v2, and on v2, MX6Q's implementation is different from MX6DL and MX6SX, MX6SL has its special implementation, and MX6Q has difference between TO1.0 and other TOs, also, we have to consider the old dtb case. So, there are more than 6 different cases we need to consider, I thought it was the best way I can figure out, could you advice if you have better idea? [The lines should be wrapped around 70 columns] I'm also a bit concerned by the readability of the code. Can we reasonably assume it must be V2_TCTL_CLK_OSC_DIV8 case if clk_get_rate(clk_per) returns 3000000? In that case, the code can be simplified a bit, something like below. Is it going to work? Shawn __raw_writel(tctl_val, timer_base + MXC_TCTL); @@ -349,9 +365,13 @@ static void __init mxc_timer_init_dt(struct device_node *np) WARN_ON(!timer_base); irq = irq_of_parse_and_map(np, 0); - clk_per = of_clk_get_by_name(np, "per"); clk_ipg = of_clk_get_by_name(np, "ipg"); + /* Try osc_per clock first, and fall back to per clock otherwise */ + clk_per = of_clk_get_by_name(np, "osc_per"); + if (!IS_ERR(clk_per)) + clk_per = of_clk_get_by_name(np, "per"); + [Anson] For i.MX6Q TO1.0, there is no GPT_3M clock for GPT, but in dtb, there is osc_per, so clk_per will be initialized by osc_per, and the clk rate read in _mxc_timer_init function will be 3000000 and go to the GPT_3M clk source path, which will NOT work for i.MX6Q TO1.0. _mxc_timer_init(irq, clk_per, clk_ipg); } CLOCKSOURCE_OF_DECLARE(mx1_timer, "fsl,imx1-gpt", mxc_timer_init_dt); diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 4ee6e77a0fdf..3f0401e27b38 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -245,6 +245,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2); + clk[IMX6QDL_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8); if (cpu_is_imx6dl()) { clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1); clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1); @@ -469,6 +470,13 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL); + /* + * The gpt_3m clock is not available on i.MX6Q TO1.0. Let's point it + * to clock gpt_ipg_per to ease the gpt driver code. + */ + if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) + clk[IMX6QDL_CLK_GPT_3M] = clk[IMX6QDL_CLK_GPT_IPG_PER]; + if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) { clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index bf92e5a351c0..c0ad839516b0 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c @@ -312,10 +317,21 @@ static void __init _mxc_timer_init(int irq, __raw_writel(0, timer_base + MXC_TCTL); __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ - if (timer_is_v2()) - tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; - else + if (timer_is_v2()) { + tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; + if (clk_get_rate(clk_per) == V2_TIMER_RATE_OSC_DIV8) { /* Is the assumption corrrect ??? */ [Anson] I am afraid that i.MX6Q TO1.0 can NOT meet it, as there is no gpt_3m available for i.MX6Q TO1.0, but we have it in dtb and clk driver. + tctl_val |= V2_TCTL_CLK_OSC_DIV8; + if (cpu_is_imx6dl() || cpu_is_imx6sx()) { + /* 24 / 8 = 3 MHz */ + __raw_writel(7 << V2_TPRER_PRE24M, timer_base + MXC_TPRER); + tctl_val |= V2_TCTL_24MEN; + } + } else { + tctl_val |= V2_TCTL_CLK_PER; + } + } else { tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; + }