| Message ID | 5F165FA1.2030301@hisilicon.com |
|---|---|
| State | New |
| Headers | show
Return-Path: <linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org> X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2001:8b0:10b:1231::1; helo=merlin.infradead.org; envelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org; receiver=<UNKNOWN>) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=hisilicon.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=merlin.20170209 header.b=iRdWcg9H; dkim-atps=neutral Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:8b0:10b:1231::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B9kTQ2cNyz9sRN for <incoming-imx@patchwork.ozlabs.org>; Tue, 21 Jul 2020 13:23:54 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Date:Message-ID:Subject:From:To: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=I5tBJiXXQUlQ28+iGmILusN7/t9fLsI3+jUqG20Exrk=; b=iRdWcg9HNRm/HhLCP/xt2X2gZn H7VNJWBkVzcG72joIMbs0mrDmCmjtC0CreQ5+x2yRE7d2VDT2Skc2DamciB2KOpshHVyaVjYd/Ink aOztjzPGxEjchcheY111nTvuJW0Vo2yJd5IPInkwF6sj7HsHqAFlV6nxzCnn5DYkBwsoiKS95VhkQ ky0vyX142n4k4WZXYqfm8JajaJL2vzxjyFw6SKrSszOkU7SSghJ8WH42S72kKdvSXzE1yu8/M0NCS DRYKzq9AHtDDgVQObZgpNefy5PCpyV80cZ3GVlsf97NcZ4I9j1tCH8FmuINTjQLg/0+n5BoUVAMgY hS1gQ8dw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jxisS-0000j7-3g; Tue, 21 Jul 2020 03:23:36 +0000 Received: from szxga04-in.huawei.com ([45.249.212.190] helo=huawei.com) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jxisH-0000fx-33 for linux-arm-kernel@lists.infradead.org; Tue, 21 Jul 2020 03:23:27 +0000 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id D9F35D81C732AF39B1EA; Tue, 21 Jul 2020 11:23:22 +0800 (CST) Received: from [10.57.101.250] (10.57.101.250) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.487.0; Tue, 21 Jul 2020 11:23:12 +0800 To: <soc@kernel.org>, "arm@kernel.org" <arm@kernel.org>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org> From: Wei Xu <xuwei5@hisilicon.com> Subject: [GIT PULL] arm: dts: hisilicon dts updates for v5.9 Message-ID: <5F165FA1.2030301@hisilicon.com> Date: Tue, 21 Jul 2020 11:23:13 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 MIME-Version: 1.0 X-Originating-IP: [10.57.101.250] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200720_232325_490560_3844661D X-CRM114-Status: UNSURE ( 7.89 ) X-CRM114-Notice: Please train this message. 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[GIT,PULL] arm: dts: hisilicon dts updates for v5.9
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Hi ARM-SoC team, Please consider to pull the following changes. Thanks! Best Regards, Wei --- The following changes since commit b3a9e3b9622ae10064826dccb4f7a52bd88c7407: Linux 5.8-rc1 (2020-06-14 12:45:04 -0700) are available in the Git repository at: git://github.com/hisilicon/linux-hisi.git tags/hisi-arm32-dt-for-5.9 for you to fetch changes up to 5720fcdc2e5af74e51c5e3102fcefd9fb061a666: ARM: dts: hisilicon: Align L2 cache-controller nodename with dtschema (2020-07-17 10:09:21 +0800) ---------------------------------------------------------------- ARM: DT: Hisilicon ARM32 SoCs updates for v5.9 - Update L2 cache controller nodes to fix dtschema validator warnings for hi3620 and hix5hd2 ---------------------------------------------------------------- Krzysztof Kozlowski (1): ARM: dts: hisilicon: Align L2 cache-controller nodename with dtschema arch/arm/boot/dts/hi3620.dtsi | 2 +- arch/arm/boot/dts/hisi-x5hd2.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)