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Wed, 24 Jun 2020 08:05:25 -0700 (PDT) From: Sven Van Asbroeck X-Google-Original-From: Sven Van Asbroeck To: shawnguo@kernel.org, fugang.duan@nxp.com Subject: [PATCH v2] ARM: imx6plus: enable internal routing of clk_enet_ref where possible Date: Wed, 24 Jun 2020 11:05:21 -0400 Message-Id: <20200624150521.12196-1-TheSven73@gmail.com> X-Mailer: git-send-email 2.17.1 X-Spam-Note: CRM114 invocation failed X-Spam-Score: 0.1 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:844 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit [thesven73[at]gmail.com] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [thesven73[at]gmail.com] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sascha Hauer , linux-kernel@vger.kernel.org, NXP Linux Team , Pengutronix Kernel Team , Fabio Estevam , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org On imx6, the ethernet reference clock (clk_enet_ref) can be generated by either the imx6, or an external source (e.g. an oscillator or the PHY). When generated by the imx6, the clock source (from ANATOP) must be routed to the input of clk_enet_ref via two pads on the SoC, typically via a dedicated track on the PCB. On an imx6 plus however, there is a new setting which enables this clock to be routed internally on the SoC, from its ANATOP clock source, straight to clk_enet_ref, without having to go through the SoC pads. Board designs where the clock is generated by the imx6 should not be affected by routing the clock internally. Therefore on a plus, we can enable internal routing by default. Signed-off-by: Sven Van Asbroeck --- v1 -> v2: - Fabio Estevam: use of_machine_is_compatible() to determine if we are running on an imx6 plus. To: Shawn Guo To: Andy Duan Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org arch/arm/mach-imx/mach-imx6q.c | 18 ++++++++++++++++++ include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 + 2 files changed, 19 insertions(+) diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 85c084a716ab..2380329ed0b2 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -203,6 +203,24 @@ static void __init imx6q_1588_init(void) else pr_err("failed to find fsl,imx6q-iomuxc-gpr regmap\n"); + /* + * On imx6 plus, enet_ref from ANATOP/CCM can be internally routed to + * be the PTP clock source, instead of having to be routed through + * pads. + * Board designs which route the ANATOP/CCM clock through pads are + * unaffected when routing happens internally. So on these designs, + * route internally by default. + */ + if (clksel == IMX6Q_GPR1_ENET_CLK_SEL_ANATOP && cpu_is_imx6q() && + of_machine_is_compatible("fsl,imx6qp")) { + if (!IS_ERR(gpr)) + regmap_update_bits(gpr, IOMUXC_GPR5, + IMX6Q_GPR5_ENET_TXCLK_SEL, + IMX6Q_GPR5_ENET_TXCLK_SEL); + else + pr_err("failed to find fsl,imx6q-iomuxc-gpr regmap\n"); + } + clk_put(enet_ref); put_ptp_clk: clk_put(ptp_clk); diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index d4b5e527a7a3..eb65d48da0df 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -240,6 +240,7 @@ #define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0) #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) +#define IMX6Q_GPR5_ENET_TXCLK_SEL BIT(9) #define IMX6Q_GPR5_SATA_SW_PD BIT(10) #define IMX6Q_GPR5_SATA_SW_RST BIT(11)