| Message ID | 20200613201703.16788-1-TheSven73@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v1] ARM: imx6plus: enable internal routing of clk_enet_ref where possible | expand |
Hi Fugang, Can you take a look at this patch? Thanks! Shawn On Sat, Jun 13, 2020 at 04:17:03PM -0400, Sven Van Asbroeck wrote: > On imx6, the ethernet reference clock (clk_enet_ref) can be generated > by either the imx6, or an external source (e.g. an oscillator or the > PHY). When generated by the imx6, the clock source (from ANATOP) > must be routed to the input of clk_enet_ref via two pads on the SoC, > typically via a dedicated track on the PCB. > > On an imx6 plus however, there is a new setting which enables this > clock to be routed internally on the SoC, from its ANATOP clock > source, straight to clk_enet_ref, without having to go through > the SoC pads. > > Board designs where the clock is generated by the imx6 should not > be affected by routing the clock internally. Therefore on a plus, > we can enable internal routing by default. > > To: Shawn Guo <shawnguo@kernel.org> > Cc: Sascha Hauer <s.hauer@pengutronix.de> > Cc: Pengutronix Kernel Team <kernel@pengutronix.de> > Cc: Fabio Estevam <festevam@gmail.com> > Cc: NXP Linux Team <linux-imx@nxp.com> > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Signed-off-by: Sven Van Asbroeck <TheSven73@gmail.com> > --- > arch/arm/mach-imx/mach-imx6q.c | 18 ++++++++++++++++++ > include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 + > 2 files changed, 19 insertions(+) > > Tree: next-20200613 > > diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c > index 85c084a716ab..4d22567bb650 100644 > --- a/arch/arm/mach-imx/mach-imx6q.c > +++ b/arch/arm/mach-imx/mach-imx6q.c > @@ -203,6 +203,24 @@ static void __init imx6q_1588_init(void) > else > pr_err("failed to find fsl,imx6q-iomuxc-gpr regmap\n"); > > + /* > + * On imx6 plus, enet_ref from ANATOP/CCM can be internally routed to > + * be the PTP clock source, instead of having to be routed through > + * pads. > + * Board designs which route the ANATOP/CCM clock through pads are > + * unaffected when routing happens internally. So on these designs, > + * route internally by default. > + */ > + if (clksel == IMX6Q_GPR1_ENET_CLK_SEL_ANATOP && cpu_is_imx6q() && > + imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) { > + if (!IS_ERR(gpr)) > + regmap_update_bits(gpr, IOMUXC_GPR5, > + IMX6Q_GPR5_ENET_TXCLK_SEL, > + IMX6Q_GPR5_ENET_TXCLK_SEL); > + else > + pr_err("failed to find fsl,imx6q-iomuxc-gpr regmap\n"); > + } > + > clk_put(enet_ref); > put_ptp_clk: > clk_put(ptp_clk); > diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h > index d4b5e527a7a3..eb65d48da0df 100644 > --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h > +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h > @@ -240,6 +240,7 @@ > #define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0) > > #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) > +#define IMX6Q_GPR5_ENET_TXCLK_SEL BIT(9) > #define IMX6Q_GPR5_SATA_SW_PD BIT(10) > #define IMX6Q_GPR5_SATA_SW_RST BIT(11) > > -- > 2.17.1 >
Hi Sven, On Sat, Jun 13, 2020 at 5:17 PM Sven Van Asbroeck <thesven73@gmail.com> wrote: > + /* > + * On imx6 plus, enet_ref from ANATOP/CCM can be internally routed to > + * be the PTP clock source, instead of having to be routed through > + * pads. > + * Board designs which route the ANATOP/CCM clock through pads are > + * unaffected when routing happens internally. So on these designs, > + * route internally by default. > + */ > + if (clksel == IMX6Q_GPR1_ENET_CLK_SEL_ANATOP && cpu_is_imx6q() && > + imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) { You should limit this to imx6 quad plus only, so you would better check against "fsl,imx6qp".
Hi Fabio, On Tue, Jun 23, 2020 at 10:19 AM Fabio Estevam <festevam@gmail.com> wrote: > > You should limit this to imx6 quad plus only, so you would better > check against "fsl,imx6qp". Excellent suggestion, thank you ! I tried to determine if running on a plus by using the method from imx6q_init_machine(). But yes, checking for "fsl,imx6qp" sounds much more elegant.
From: Shawn Guo <shawnguo@kernel.org> Sent: Tuesday, June 23, 2020 7:54 PM > Hi Fugang, > > Can you take a look at this patch? Thanks! > The patch looks good. Reviewed-by: Fugang Duan <fugang.duan@nxp.com> > Shawn > > On Sat, Jun 13, 2020 at 04:17:03PM -0400, Sven Van Asbroeck wrote: > > On imx6, the ethernet reference clock (clk_enet_ref) can be generated > > by either the imx6, or an external source (e.g. an oscillator or the > > PHY). When generated by the imx6, the clock source (from ANATOP) must > > be routed to the input of clk_enet_ref via two pads on the SoC, > > typically via a dedicated track on the PCB. > > > > On an imx6 plus however, there is a new setting which enables this > > clock to be routed internally on the SoC, from its ANATOP clock > > source, straight to clk_enet_ref, without having to go through the SoC > > pads. > > > > Board designs where the clock is generated by the imx6 should not be > > affected by routing the clock internally. Therefore on a plus, we can > > enable internal routing by default. > > > > To: Shawn Guo <shawnguo@kernel.org> > > Cc: Sascha Hauer <s.hauer@pengutronix.de> > > Cc: Pengutronix Kernel Team <kernel@pengutronix.de> > > Cc: Fabio Estevam <festevam@gmail.com> > > Cc: NXP Linux Team <linux-imx@nxp.com> > > Cc: linux-arm-kernel@lists.infradead.org > > Cc: linux-kernel@vger.kernel.org > > Signed-off-by: Sven Van Asbroeck <TheSven73@gmail.com> > > --- > > arch/arm/mach-imx/mach-imx6q.c | 18 > ++++++++++++++++++ > > include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 + > > 2 files changed, 19 insertions(+) > > > > Tree: next-20200613 > > > > diff --git a/arch/arm/mach-imx/mach-imx6q.c > > b/arch/arm/mach-imx/mach-imx6q.c index 85c084a716ab..4d22567bb650 > > 100644 > > --- a/arch/arm/mach-imx/mach-imx6q.c > > +++ b/arch/arm/mach-imx/mach-imx6q.c > > @@ -203,6 +203,24 @@ static void __init imx6q_1588_init(void) > > else > > pr_err("failed to find fsl,imx6q-iomuxc-gpr regmap\n"); > > > > + /* > > + * On imx6 plus, enet_ref from ANATOP/CCM can be internally > routed to > > + * be the PTP clock source, instead of having to be routed through > > + * pads. > > + * Board designs which route the ANATOP/CCM clock through pads > are > > + * unaffected when routing happens internally. So on these designs, > > + * route internally by default. > > + */ > > + if (clksel == IMX6Q_GPR1_ENET_CLK_SEL_ANATOP && > cpu_is_imx6q() && > > + imx_get_soc_revision() >= > IMX_CHIP_REVISION_2_0) { > > + if (!IS_ERR(gpr)) > > + regmap_update_bits(gpr, IOMUXC_GPR5, > > + > IMX6Q_GPR5_ENET_TXCLK_SEL, > > + > IMX6Q_GPR5_ENET_TXCLK_SEL); > > + else > > + pr_err("failed to find fsl,imx6q-iomuxc-gpr > regmap\n"); > > + } > > + > > clk_put(enet_ref); > > put_ptp_clk: > > clk_put(ptp_clk); > > diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h > > b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h > > index d4b5e527a7a3..eb65d48da0df 100644 > > --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h > > +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h > > @@ -240,6 +240,7 @@ > > #define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0) > > > > #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) > > +#define IMX6Q_GPR5_ENET_TXCLK_SEL BIT(9) > > #define IMX6Q_GPR5_SATA_SW_PD BIT(10) > > #define IMX6Q_GPR5_SATA_SW_RST BIT(11) > > > > -- > > 2.17.1 > >
Hi Andy, On Tue, Jun 23, 2020 at 9:40 PM Andy Duan <fugang.duan@nxp.com> wrote: > > The patch looks good. > Reviewed-by: Fugang Duan <fugang.duan@nxp.com> Thank you ! To check we're on a plus, the patch uses: cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0 Fabio Estevam suggested that perhaps checking of_machine_is_compatible("fsl,imx6qp") might be preferable. What is your opinion on this?
From: Sven Van Asbroeck <thesven73@gmail.com> Sent: Wednesday, June 24, 2020 10:56 AM > Hi Andy, > > On Tue, Jun 23, 2020 at 9:40 PM Andy Duan <fugang.duan@nxp.com> wrote: > > > > The patch looks good. > > Reviewed-by: Fugang Duan <fugang.duan@nxp.com> > > Thank you ! > > To check we're on a plus, the patch uses: > cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0 > > Fabio Estevam suggested that perhaps checking > of_machine_is_compatible("fsl,imx6qp") > might be preferable. What is your opinion on this? Yes, I also think of_machine_is_compatible() is much better. Thanks.
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 85c084a716ab..4d22567bb650 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -203,6 +203,24 @@ static void __init imx6q_1588_init(void) else pr_err("failed to find fsl,imx6q-iomuxc-gpr regmap\n"); + /* + * On imx6 plus, enet_ref from ANATOP/CCM can be internally routed to + * be the PTP clock source, instead of having to be routed through + * pads. + * Board designs which route the ANATOP/CCM clock through pads are + * unaffected when routing happens internally. So on these designs, + * route internally by default. + */ + if (clksel == IMX6Q_GPR1_ENET_CLK_SEL_ANATOP && cpu_is_imx6q() && + imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) { + if (!IS_ERR(gpr)) + regmap_update_bits(gpr, IOMUXC_GPR5, + IMX6Q_GPR5_ENET_TXCLK_SEL, + IMX6Q_GPR5_ENET_TXCLK_SEL); + else + pr_err("failed to find fsl,imx6q-iomuxc-gpr regmap\n"); + } + clk_put(enet_ref); put_ptp_clk: clk_put(ptp_clk); diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index d4b5e527a7a3..eb65d48da0df 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -240,6 +240,7 @@ #define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0) #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) +#define IMX6Q_GPR5_ENET_TXCLK_SEL BIT(9) #define IMX6Q_GPR5_SATA_SW_PD BIT(10) #define IMX6Q_GPR5_SATA_SW_RST BIT(11)
On imx6, the ethernet reference clock (clk_enet_ref) can be generated by either the imx6, or an external source (e.g. an oscillator or the PHY). When generated by the imx6, the clock source (from ANATOP) must be routed to the input of clk_enet_ref via two pads on the SoC, typically via a dedicated track on the PCB. On an imx6 plus however, there is a new setting which enables this clock to be routed internally on the SoC, from its ANATOP clock source, straight to clk_enet_ref, without having to go through the SoC pads. Board designs where the clock is generated by the imx6 should not be affected by routing the clock internally. Therefore on a plus, we can enable internal routing by default. To: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Sven Van Asbroeck <TheSven73@gmail.com> --- arch/arm/mach-imx/mach-imx6q.c | 18 ++++++++++++++++++ include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 + 2 files changed, 19 insertions(+) Tree: next-20200613