[GIT,PULL] ARM: switch to by-VA cache ops for v7 in the decompressor

Hello Russell,

Please consider the pull request below.

Regards,
Ard.

Cc: Marc Zyngier <maz@kernel.org>,
Cc: Nicolas Pitre <nico@fluxnic.net>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Linus Walleij <linus.walleij@linaro.org>

The following changes since commit bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9:

  Linux 5.6-rc1 (2020-02-09 16:08:48 -0800)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/ardb/linux.git tags/arm32-efi-cache-ops-for-rmk

for you to fetch changes up to 401b368caaecdce1cf8f05bab448172752230cb0:

  ARM: decompressor: switch to by-VA cache maintenance for v7 cores (2020-02-27 11:15:50 +0100)

----------------------------------------------------------------
ARMv7 compliant cache maintenance for the decompressor

On v7 and later cores, cache maintenance operations by set/way are only
intended to be used in the context of on/offlining a core, while it has
been taken out of the coherency domain. Any use intended to ensure that
the contents of the cache have made it to main memory is unreliable,
since cacheline migration and non-architected system caches may cause
these contents to linger elsewhere, without being visible in main memory
once the MMU and caches are disabled.

So switch to cache maintenance by virtual address for v7 and later cores.
This makes the 32-bit kernel bootable on systems with L3 system caches
that are not covered by set/way operations, such as Socionext SynQuacer.

Tony says:

  I gave these a try on top of the earlier "arm: fix Kbuild issue caused
  by per-task stack protector GCC plugin" and booting still works for
  me on armv7 including appended dtb:

  Tested-by: Tony Lindgren <tony@atomide.com>

Linus says:

  No problem, I have tested it on the following:

  - ARMv7 Cortex A9 x 2 Qualcomm APQ8060 DragonBoard
  - ARM PB11MPCore (4 x 1176)
  - ARMv7 Ux500 Cortex A9 x 2

  The PB11MPCore is again the crucial board, if it work on that
  board it works on anything, most of the time :D

  Tested-by: Linus Walleij <linus.walleij@linaro.org>

Note that the first 2 patches are shared with the efi/core branch in
TIP, which is the reason why this is sent as a pull request rather
than via the patch system.

----------------------------------------------------------------
Ard Biesheuvel (5):
      efi/arm: Work around missing cache maintenance in decompressor handover
      efi/arm: Pass start and end addresses to cache_clean_flush()
      ARM: decompressor: factor out routine to obtain the inflated image size
      ARM: decompressor: prepare cache_clean_flush for doing by-VA maintenance
      ARM: decompressor: switch to by-VA cache maintenance for v7 cores

 arch/arm/boot/compressed/head.S | 162 +++++++++++++++++++++-------------------
 1 file changed, 86 insertions(+), 76 deletions(-)

On Thu, 27 Feb 2020 at 11:42, Ard Biesheuvel <ardb@kernel.org> wrote:
>
> Hello Russell,
>
> Please consider the pull request below.
>
> Regards,
> Ard.
>
> Cc: Marc Zyngier <maz@kernel.org>,
> Cc: Nicolas Pitre <nico@fluxnic.net>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Linus Walleij <linus.walleij@linaro.org>
>
> The following changes since commit bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9:
>
>   Linux 5.6-rc1 (2020-02-09 16:08:48 -0800)
>
> are available in the Git repository at:
>
>   git://git.kernel.org/pub/scm/linux/kernel/git/ardb/linux.git tags/arm32-efi-cache-ops-for-rmk
>
> for you to fetch changes up to 401b368caaecdce1cf8f05bab448172752230cb0:
>
>   ARM: decompressor: switch to by-VA cache maintenance for v7 cores (2020-02-27 11:15:50 +0100)
>
> ----------------------------------------------------------------
> ARMv7 compliant cache maintenance for the decompressor
>
> On v7 and later cores, cache maintenance operations by set/way are only
> intended to be used in the context of on/offlining a core, while it has
> been taken out of the coherency domain. Any use intended to ensure that
> the contents of the cache have made it to main memory is unreliable,
> since cacheline migration and non-architected system caches may cause
> these contents to linger elsewhere, without being visible in main memory
> once the MMU and caches are disabled.
>
> So switch to cache maintenance by virtual address for v7 and later cores.
> This makes the 32-bit kernel bootable on systems with L3 system caches
> that are not covered by set/way operations, such as Socionext SynQuacer.
>
> Tony says:
>
>   I gave these a try on top of the earlier "arm: fix Kbuild issue caused
>   by per-task stack protector GCC plugin" and booting still works for
>   me on armv7 including appended dtb:
>
>   Tested-by: Tony Lindgren <tony@atomide.com>
>
> Linus says:
>
>   No problem, I have tested it on the following:
>
>   - ARMv7 Cortex A9 x 2 Qualcomm APQ8060 DragonBoard
>   - ARM PB11MPCore (4 x 1176)
>   - ARMv7 Ux500 Cortex A9 x 2
>
>   The PB11MPCore is again the crucial board, if it work on that
>   board it works on anything, most of the time :D
>
>   Tested-by: Linus Walleij <linus.walleij@linaro.org>
>
> Note that the first 2 patches are shared with the efi/core branch in
> TIP, which is the reason why this is sent as a pull request rather
> than via the patch system.
>
> ----------------------------------------------------------------
> Ard Biesheuvel (5):
>       efi/arm: Work around missing cache maintenance in decompressor handover
>       efi/arm: Pass start and end addresses to cache_clean_flush()
>       ARM: decompressor: factor out routine to obtain the inflated image size
>       ARM: decompressor: prepare cache_clean_flush for doing by-VA maintenance
>       ARM: decompressor: switch to by-VA cache maintenance for v7 cores
>
>  arch/arm/boot/compressed/head.S | 162 +++++++++++++++++++++-------------------
>  1 file changed, 86 insertions(+), 76 deletions(-)

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