From patchwork Tue Apr 3 06:18:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Myl=C3=A8ne_Josserand?= X-Patchwork-Id: 894445 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bootlin.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="JmW2TOVz"; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:e::133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40FfD36kvYz9s3M for ; Tue, 3 Apr 2018 16:23:15 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=JUpNKtCLTXB6DWbSJCB3hH7X3c3crk5XjDmb+3L9vEE=; b=JmW2TOVzoEHrC2 mVcoP9KMfXSgoSWqfmmyavfo7O5DXNROdti462nFh3gxKTQRVhWPOVoy10p/lBexZyhyZr6DLQLOI ZFr1DPorHHg6WG7j0M4nDfOJ1TjMO3DmEaraeG7IxG5ySWUI72OcS+Ca/NY8v6NZwgrORnJYKlsi4 icUlfxa3zlcJAmq0CHfLbm/70QI9jz8CL2tFxti/QPD2fl3AWokgptOeLvekoiG+R5Qb9MW3+zCsC yLJSF02l6U1Y5drkmS8LgCISlEwLr5KDl3mxqQGaKthgdP91rZJqDUgA3B6wCIAc5B3D75EPtN2iy gqntN4hpDpxFK4kTgjxQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1f3FLV-0006eF-3N; Tue, 03 Apr 2018 06:23:05 +0000 Received: from mail.bootlin.com ([62.4.15.54]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1f3FJY-0005G4-Ql for linux-arm-kernel@lists.infradead.org; Tue, 03 Apr 2018 06:21:09 +0000 Received: by mail.bootlin.com (Postfix, from userid 110) id 778832075F; Tue, 3 Apr 2018 08:20:53 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.0 Received: from dell-desktop.home (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.bootlin.com (Postfix) with ESMTPSA id 2024F20384; Tue, 3 Apr 2018 08:20:53 +0200 (CEST) From: =?utf-8?q?Myl=C3=A8ne_Josserand?= To: linux@armlinux.org.uk, maxime.ripard@bootlin.com, wens@csie.org, marc.zyngier@arm.com, mark.rutland@arm.com, robh+dt@kernel.org Subject: [PATCH v5 01/13] ARM: move cputype definitions into another file Date: Tue, 3 Apr 2018 08:18:24 +0200 Message-Id: <20180403061836.3926-2-mylene.josserand@bootlin.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180403061836.3926-1-mylene.josserand@bootlin.com> References: <20180403061836.3926-1-mylene.josserand@bootlin.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180402_232105_242809_196B646A X-CRM114-Status: GOOD ( 13.50 ) X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, quentin.schulz@bootlin.com, linux-kernel@vger.kernel.org, clabbe.montjoie@gmail.com, thomas.petazzoni@bootlin.com, mylene.josserand@bootlin.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org To add the support for SMP on sun8i-a83t, we will use some definitions in an assembly file so move definitions into another file to separate C functions and macro defintions. Signed-off-by: Mylène Josserand --- arch/arm/include/asm/cputype.h | 94 +----------------------------------- arch/arm/include/asm/cputype_def.h | 98 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 99 insertions(+), 93 deletions(-) create mode 100644 arch/arm/include/asm/cputype_def.h diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index cb546425da8a..4cb26e840a58 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -4,99 +4,7 @@ #include #include - -#define CPUID_ID 0 -#define CPUID_CACHETYPE 1 -#define CPUID_TCM 2 -#define CPUID_TLBTYPE 3 -#define CPUID_MPUIR 4 -#define CPUID_MPIDR 5 -#define CPUID_REVIDR 6 - -#ifdef CONFIG_CPU_V7M -#define CPUID_EXT_PFR0 0x40 -#define CPUID_EXT_PFR1 0x44 -#define CPUID_EXT_DFR0 0x48 -#define CPUID_EXT_AFR0 0x4c -#define CPUID_EXT_MMFR0 0x50 -#define CPUID_EXT_MMFR1 0x54 -#define CPUID_EXT_MMFR2 0x58 -#define CPUID_EXT_MMFR3 0x5c -#define CPUID_EXT_ISAR0 0x60 -#define CPUID_EXT_ISAR1 0x64 -#define CPUID_EXT_ISAR2 0x68 -#define CPUID_EXT_ISAR3 0x6c -#define CPUID_EXT_ISAR4 0x70 -#define CPUID_EXT_ISAR5 0x74 -#else -#define CPUID_EXT_PFR0 "c1, 0" -#define CPUID_EXT_PFR1 "c1, 1" -#define CPUID_EXT_DFR0 "c1, 2" -#define CPUID_EXT_AFR0 "c1, 3" -#define CPUID_EXT_MMFR0 "c1, 4" -#define CPUID_EXT_MMFR1 "c1, 5" -#define CPUID_EXT_MMFR2 "c1, 6" -#define CPUID_EXT_MMFR3 "c1, 7" -#define CPUID_EXT_ISAR0 "c2, 0" -#define CPUID_EXT_ISAR1 "c2, 1" -#define CPUID_EXT_ISAR2 "c2, 2" -#define CPUID_EXT_ISAR3 "c2, 3" -#define CPUID_EXT_ISAR4 "c2, 4" -#define CPUID_EXT_ISAR5 "c2, 5" -#endif - -#define MPIDR_SMP_BITMASK (0x3 << 30) -#define MPIDR_SMP_VALUE (0x2 << 30) - -#define MPIDR_MT_BITMASK (0x1 << 24) - -#define MPIDR_HWID_BITMASK 0xFFFFFF - -#define MPIDR_INVALID (~MPIDR_HWID_BITMASK) - -#define MPIDR_LEVEL_BITS 8 -#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) -#define MPIDR_LEVEL_SHIFT(level) (MPIDR_LEVEL_BITS * level) - -#define MPIDR_AFFINITY_LEVEL(mpidr, level) \ - ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK) - -#define ARM_CPU_IMP_ARM 0x41 -#define ARM_CPU_IMP_DEC 0x44 -#define ARM_CPU_IMP_INTEL 0x69 - -/* ARM implemented processors */ -#define ARM_CPU_PART_ARM1136 0x4100b360 -#define ARM_CPU_PART_ARM1156 0x4100b560 -#define ARM_CPU_PART_ARM1176 0x4100b760 -#define ARM_CPU_PART_ARM11MPCORE 0x4100b020 -#define ARM_CPU_PART_CORTEX_A8 0x4100c080 -#define ARM_CPU_PART_CORTEX_A9 0x4100c090 -#define ARM_CPU_PART_CORTEX_A5 0x4100c050 -#define ARM_CPU_PART_CORTEX_A7 0x4100c070 -#define ARM_CPU_PART_CORTEX_A12 0x4100c0d0 -#define ARM_CPU_PART_CORTEX_A17 0x4100c0e0 -#define ARM_CPU_PART_CORTEX_A15 0x4100c0f0 -#define ARM_CPU_PART_MASK 0xff00fff0 - -/* DEC implemented cores */ -#define ARM_CPU_PART_SA1100 0x4400a110 - -/* Intel implemented cores */ -#define ARM_CPU_PART_SA1110 0x6900b110 -#define ARM_CPU_REV_SA1110_A0 0 -#define ARM_CPU_REV_SA1110_B0 4 -#define ARM_CPU_REV_SA1110_B1 5 -#define ARM_CPU_REV_SA1110_B2 6 -#define ARM_CPU_REV_SA1110_B4 8 - -#define ARM_CPU_XSCALE_ARCH_MASK 0xe000 -#define ARM_CPU_XSCALE_ARCH_V1 0x2000 -#define ARM_CPU_XSCALE_ARCH_V2 0x4000 -#define ARM_CPU_XSCALE_ARCH_V3 0x6000 - -/* Qualcomm implemented cores */ -#define ARM_CPU_PART_SCORPION 0x510002d0 +#include extern unsigned int processor_id; diff --git a/arch/arm/include/asm/cputype_def.h b/arch/arm/include/asm/cputype_def.h new file mode 100644 index 000000000000..3a62ea13dc35 --- /dev/null +++ b/arch/arm/include/asm/cputype_def.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_ARM_CPUTYPEDEF_H +#define __ASM_ARM_CPUTYPEDEF_H + +#define CPUID_ID 0 +#define CPUID_CACHETYPE 1 +#define CPUID_TCM 2 +#define CPUID_TLBTYPE 3 +#define CPUID_MPUIR 4 +#define CPUID_MPIDR 5 +#define CPUID_REVIDR 6 + +#ifdef CONFIG_CPU_V7M +#define CPUID_EXT_PFR0 0x40 +#define CPUID_EXT_PFR1 0x44 +#define CPUID_EXT_DFR0 0x48 +#define CPUID_EXT_AFR0 0x4c +#define CPUID_EXT_MMFR0 0x50 +#define CPUID_EXT_MMFR1 0x54 +#define CPUID_EXT_MMFR2 0x58 +#define CPUID_EXT_MMFR3 0x5c +#define CPUID_EXT_ISAR0 0x60 +#define CPUID_EXT_ISAR1 0x64 +#define CPUID_EXT_ISAR2 0x68 +#define CPUID_EXT_ISAR3 0x6c +#define CPUID_EXT_ISAR4 0x70 +#define CPUID_EXT_ISAR5 0x74 +#else +#define CPUID_EXT_PFR0 "c1, 0" +#define CPUID_EXT_PFR1 "c1, 1" +#define CPUID_EXT_DFR0 "c1, 2" +#define CPUID_EXT_AFR0 "c1, 3" +#define CPUID_EXT_MMFR0 "c1, 4" +#define CPUID_EXT_MMFR1 "c1, 5" +#define CPUID_EXT_MMFR2 "c1, 6" +#define CPUID_EXT_MMFR3 "c1, 7" +#define CPUID_EXT_ISAR0 "c2, 0" +#define CPUID_EXT_ISAR1 "c2, 1" +#define CPUID_EXT_ISAR2 "c2, 2" +#define CPUID_EXT_ISAR3 "c2, 3" +#define CPUID_EXT_ISAR4 "c2, 4" +#define CPUID_EXT_ISAR5 "c2, 5" +#endif + +#define MPIDR_SMP_BITMASK (0x3 << 30) +#define MPIDR_SMP_VALUE (0x2 << 30) + +#define MPIDR_MT_BITMASK (0x1 << 24) + +#define MPIDR_HWID_BITMASK 0xFFFFFF + +#define MPIDR_INVALID (~MPIDR_HWID_BITMASK) + +#define MPIDR_LEVEL_BITS 8 +#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) +#define MPIDR_LEVEL_SHIFT(level) (MPIDR_LEVEL_BITS * level) + +#define MPIDR_AFFINITY_LEVEL(mpidr, level) \ + ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK) + +#define ARM_CPU_IMP_ARM 0x41 +#define ARM_CPU_IMP_DEC 0x44 +#define ARM_CPU_IMP_INTEL 0x69 + +/* ARM implemented processors */ +#define ARM_CPU_PART_ARM1136 0x4100b360 +#define ARM_CPU_PART_ARM1156 0x4100b560 +#define ARM_CPU_PART_ARM1176 0x4100b760 +#define ARM_CPU_PART_ARM11MPCORE 0x4100b020 +#define ARM_CPU_PART_CORTEX_A8 0x4100c080 +#define ARM_CPU_PART_CORTEX_A9 0x4100c090 +#define ARM_CPU_PART_CORTEX_A5 0x4100c050 +#define ARM_CPU_PART_CORTEX_A7 0x4100c070 +#define ARM_CPU_PART_CORTEX_A12 0x4100c0d0 +#define ARM_CPU_PART_CORTEX_A17 0x4100c0e0 +#define ARM_CPU_PART_CORTEX_A15 0x4100c0f0 +#define ARM_CPU_PART_MASK 0xff00fff0 + +/* DEC implemented cores */ +#define ARM_CPU_PART_SA1100 0x4400a110 + +/* Intel implemented cores */ +#define ARM_CPU_PART_SA1110 0x6900b110 +#define ARM_CPU_REV_SA1110_A0 0 +#define ARM_CPU_REV_SA1110_B0 4 +#define ARM_CPU_REV_SA1110_B1 5 +#define ARM_CPU_REV_SA1110_B2 6 +#define ARM_CPU_REV_SA1110_B4 8 + +#define ARM_CPU_XSCALE_ARCH_MASK 0xe000 +#define ARM_CPU_XSCALE_ARCH_V1 0x2000 +#define ARM_CPU_XSCALE_ARCH_V2 0x4000 +#define ARM_CPU_XSCALE_ARCH_V3 0x6000 + +/* Qualcomm implemented cores */ +#define ARM_CPU_PART_SCORPION 0x510002d0 + +#endif