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[78.51.244.199]) by smtp.gmail.com with ESMTPSA id f21sm2881165wra.5.2017.06.22.12.35.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 22 Jun 2017 12:35:38 -0700 (PDT) Date: Thu, 22 Jun 2017 21:35:35 +0200 From: Robert Richter To: Will Deacon Subject: Re: [Devel] [PATCH v9 0/3] Cavium ThunderX2 SMMUv3 errata workarounds Message-ID: <20170622193535.GA10237@rric.localdomain> References: <1498133138-20244-1-git-send-email-gakula@caviumnetworks.com> <20170622182257.GI15336@arm.com> <20170622185822.GK15336@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20170622185822.GK15336@arm.com> User-Agent: Mutt/1.5.23 (2014-03-12) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170622_123556_784566_84D8857A X-CRM114-Status: GOOD ( 21.42 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [2a00:1450:400c:c0c:0:0:0:244 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (rric.net[at]gmail.com) 0.0 HEADER_FROM_DIFFERENT_DOMAINS From and EnvelopeFrom 2nd level mail domains are different -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 FREEMAIL_FORGED_FROMDOMAIN 2nd level domains in From and EnvelopeFrom freemail headers are different X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robh@kernel.org, lorenzo.pieralisi@arm.com, linu.cherian@cavium.com, robert.richter@cavium.com, catalin.marinas@arm.com, Geetha sowjanya , rjw@rjwysocki.net, linux-kernel@vger.kernel.org, geethasowjanya.akula@gmail.com, linux-acpi@vger.kernel.org, iommu@lists.linux-foundation.org, jcm@redhat.com, sgoutham@cavium.com, Charles.Garcia-Tobin@arm.com, robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org, devel@acpica.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org On 22.06.17 19:58:22, Will Deacon wrote: > On Thu, Jun 22, 2017 at 07:22:57PM +0100, Will Deacon wrote: > > On Thu, Jun 22, 2017 at 05:35:35PM +0530, Geetha sowjanya wrote: > > > Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. > > > 1. Errata ID #74 > > > SMMU register alias Page 1 is not implemented > > > 2. Errata ID #126 > > > SMMU doesnt support unique IRQ lines and also MSI for gerror, > > > eventq and cmdq-sync > > > > > > The following patchset does software workaround for these two erratas. > > > > I've picked up the first two patches, and left comments on the final patch. > > ... except that it doesn't build: > > > drivers/acpi/arm64/iort.c: In function ‘arm_smmu_v3_resource_size’: > drivers/acpi/arm64/iort.c:837:21: error: ‘ACPI_IORT_SMMU_V3_CAVIUM_CN99XX’ undeclared (first use in this function) > if (smmu->model == ACPI_IORT_SMMU_V3_CAVIUM_CN99XX) > ^ > drivers/acpi/arm64/iort.c:837:21: note: each undeclared identifier is reported only once for each function it appears in > make[4]: *** [drivers/acpi/arm64/iort.o] Error 1 > > > I don't see ACPI_IORT_SMMU_V3_CAVIUM_CN99XX defined, even in linux-next. > > What's the plan here? It is defined already in acpica and we actually waiting for the acpi maintainers to include it: https://github.com/acpica/acpica/commit/d00a4eb86e64 We could add /* Until ACPICA headers cover IORT rev. C */ #ifndef ACPI_IORT_SMMU_V3_CAVIUM_CN99XX #define ACPI_IORT_SMMU_V3_CAVIUM_CN99XX 0x2 #endif to both files: drivers/acpi/arm64/iort.c drivers/iommu/arm-smmu-v3.c This is similar to what Robin did. (I checked arm64 include files and the closest was arch/arm64/include/asm/acpi.h, bug this seems not really suitable to me.) I have created a separate patch to be applied at first below. We can revert it after acpica was updated. -Robert From ad7f0112a2a71059c32bd315835c33cc7bc660b8 Mon Sep 17 00:00:00 2001 From: Robert Richter Date: Thu, 22 Jun 2017 21:20:54 +0200 Subject: [PATCH] iommu/arm-smmu-v3: Add temporary Cavium SMMU-V3 model nuber definitions The model number is already defined in acpica and we actually waiting for the acpi maintainers to include it: https://github.com/acpica/acpica/commit/d00a4eb86e64 Adding those temporary definitions until the change makes it into include/acpi/actbl2.h. Signed-off-by: Robert Richter --- drivers/acpi/arm64/iort.c | 5 +++++ drivers/iommu/arm-smmu-v3.c | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index 797b28dc7b34..15491237a657 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -31,6 +31,11 @@ #define IORT_IOMMU_TYPE ((1 << ACPI_IORT_NODE_SMMU) | \ (1 << ACPI_IORT_NODE_SMMU_V3)) +/* Until ACPICA headers cover IORT rev. C */ +#ifndef ACPI_IORT_SMMU_V3_CAVIUM_CN99XX +#define ACPI_IORT_SMMU_V3_CAVIUM_CN99XX 0x2 +#endif + struct iort_its_msi_chip { struct list_head list; struct fwnode_handle *fw_node; diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 380969aa60d5..c759dfa7442d 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -412,6 +412,11 @@ #define MSI_IOVA_BASE 0x8000000 #define MSI_IOVA_LENGTH 0x100000 +/* Until ACPICA headers cover IORT rev. C */ +#ifndef ACPI_IORT_SMMU_V3_CAVIUM_CN99XX +#define ACPI_IORT_SMMU_V3_CAVIUM_CN99XX 0x2 +#endif + static bool disable_bypass; module_param_named(disable_bypass, disable_bypass, bool, S_IRUGO); MODULE_PARM_DESC(disable_bypass,