From patchwork Tue Jun 6 00:54:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 771573 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3whYRn4yl5z9s74 for ; Tue, 6 Jun 2017 11:06:45 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="jgsPgXZG"; dkim-atps=neutral DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=WuG45gE7Ws6ooqhTuTVR1UpEanMRkMpwX9wJK5oSpRI=; b=jgsPgXZGUGYJ5Y 4FmgmgsDLkpEj4c2Zi3iicHWXgshvaXiHFl4K2PfrK6UepiBVfUAr/gPWwcRbLs0ixW25cx9zOTq/ 1RRmLHa44J3ed9vvdTVtSR+u6JSxjhF1voPI6BEwLqCC/ZFWu8FoMvPzFvKHExjAJmrPoOtFd2psI MNGzSRUPkF8/+NuuBuxFKSoN+A8jjcsNoK7r7YygbfQWfWaEHDuhMLbHu20npFuefccjyi4Elcm7o TS57kD/TSpVk4yE/F3Dxo7Zg0TMmZ74NS1p8lwLCu+I63kP6jdlRiWJ6g2aTXZBKjG7FCWYIJ7Dl/ NkaP4/WMribpxdZ/T8uA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dI2xC-0005hp-J2; Tue, 06 Jun 2017 01:06:38 +0000 Received: from mx2.suse.de ([195.135.220.15] helo=mx1.suse.de) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1dI2nA-0006QB-S0 for linux-arm-kernel@lists.infradead.org; Tue, 06 Jun 2017 00:56:21 +0000 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 47CE3ADB9; Tue, 6 Jun 2017 00:55:17 +0000 (UTC) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 19/28] dt-bindings: arm: cpus: Add S500 enable-method Date: Tue, 6 Jun 2017 02:54:17 +0200 Message-Id: <20170606005426.26446-20-afaerber@suse.de> X-Mailer: git-send-email 2.12.3 In-Reply-To: <20170606005426.26446-1-afaerber@suse.de> References: <20170606005426.26446-1-afaerber@suse.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170605_175617_338340_8F274F7A X-CRM114-Status: UNSURE ( 8.15 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [195.135.220.15 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , support@lemaker.org, =?UTF-8?q?=E5=BC=A0=E5=A4=A9=E7=9B=8A?= , devicetree@vger.kernel.org, 96boards@ucrobotics.com, linux-kernel@vger.kernel.org, Thomas Liau , Rob Herring , mp-cs@actions-semi.com, =?UTF-8?q?=E5=88=98=E7=82=9C?= , =?UTF-8?q?Andreas=20F=C3=A4rber?= , =?UTF-8?q?=E5=BC=A0=E4=B8=9C=E9=A3=8E?= Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org The Actions Semi S500 SoC requires a special secondary CPU boot procedure. Acked-by: Rob Herring Signed-off-by: Andreas Färber --- v3 -> v4: Unchanged v3: new Documentation/devicetree/bindings/arm/cpus.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 2713aadb7411..ad1913bea8d7 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -193,6 +193,7 @@ nodes to be present and contain the properties described below. "spin-table" # On ARM 32-bit systems this property is optional and can be one of: + "actions,s500-smp" "allwinner,sun6i-a31" "allwinner,sun8i-a23" "arm,realview-smp"