From patchwork Wed Dec 4 14:41:47 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezequiel Garcia X-Patchwork-Id: 296530 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from casper.infradead.org (unknown [IPv6:2001:770:15f::2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 415BB2C0077 for ; Thu, 5 Dec 2013 01:42:30 +1100 (EST) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VoDed-0004iT-Hz; Wed, 04 Dec 2013 14:42:19 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VoDeb-0006Cg-70; Wed, 04 Dec 2013 14:42:17 +0000 Received: from top.free-electrons.com ([176.31.233.9] helo=mail.free-electrons.com) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VoDeX-0006Ah-KO; Wed, 04 Dec 2013 14:42:14 +0000 Received: by mail.free-electrons.com (Postfix, from userid 106) id 8A59279D; Wed, 4 Dec 2013 15:41:43 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.3.2 Received: from localhost (unknown [190.2.98.212]) by mail.free-electrons.com (Postfix) with ESMTPSA id 8535271B; Wed, 4 Dec 2013 15:41:40 +0100 (CET) Date: Wed, 4 Dec 2013 11:41:47 -0300 From: Ezequiel Garcia To: Arnaud Ebalard Subject: Re: [PATCH v5 00/14] Armada 370/XP NAND support Message-ID: <20131204144146.GC2486@localhost> References: <87zjopd240.fsf@natisbad.org> <87wqjtbm8r.fsf@natisbad.org> <20131128185040.GA13182@localhost> <87bo12kcyt.fsf@natisbad.org> <20131202103305.GB2466@localhost> <87siubneuf.fsf@natisbad.org> <20131203002225.GA5333@localhost> <87ob4xbs8l.fsf@natisbad.org> <87iov5aapx.fsf@natisbad.org> <20131204142009.GB2486@localhost> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20131204142009.GB2486@localhost> User-Agent: Mutt/1.5.21 (2010-09-15) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131204_094213_867983_180D16FD X-CRM114-Status: GOOD ( 17.08 ) X-Spam-Score: -1.2 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.7 SPF_SOFTFAIL SPF: sender does not match SPF record (softfail) -0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Lior Amsalem , Thomas Petazzoni , Jason Cooper , linux-mtd@lists.infradead.org, Gregory Clement , Brian Norris , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org On Wed, Dec 04, 2013 at 11:20:09AM -0300, Ezequiel Garcia wrote: > On Tue, Dec 03, 2013 at 10:25:14PM +0100, Arnaud Ebalard wrote: [..] > > Erasing failed write from 0x0a0000 to 0x0bffff > > Writing data to block 6 at offset 0xc0000 > > [ 451.115171] pxa3xx-nand d00d0000.nand: Ready time out!!! > > libmtd: error!: cannot write 2048 bytes to mtd4 (eraseblock 6, offset 2048) > > error 5 (Input/output error) > > Erasing failed write from 0x0c0000 to 0x0dffff > > Writing data to block 7 at offset 0xe0000 > > > > > > So, let me confirm this: you have systematically obtained a "Ready > timeout" when writing to the device, on every single write to a page, > correct? > > I'll prepare a patch against the branch we're working that adds lots of > pr_info(). It'll be very annoying for you, but it's the only way I can > think of, to get the driver's dirty inner sequence and to see *where* > is failing. > [..] And here's the patch, along with instructions... commit cc7999a922bf3c09ddc65effb11de6fc5ea88b1c Author: Ezequiel Garcia Date: Wed Dec 4 11:27:04 2013 -0300 mtd: nand: pxa3xx: Add debug messages Need CONFIG_DYNAMIC_DEBUG=y and then: $ mount -t debugfs debugfs /sys/kernel/debug/ $ cd /sys/kernel/debug/dynamic_debug/ $ echo "file drivers/mtd/nand/pxa3xx_nand.c +p" > control Signed-off-by: Ezequiel Garcia diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 038cf5d..1744599 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -616,6 +616,7 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid) if (status & ready) { info->state = STATE_READY; is_ready = 1; + pr_debug("Status: ready\n"); } if (status & NDSR_WRCMDREQ) { @@ -631,6 +632,11 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid) * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored * but each NDCBx register can be read. */ + pr_debug("Command0 0x%x\n", info->ndcb0); + pr_debug("Command1 0x%x\n", info->ndcb1); + pr_debug("Command2 0x%x\n", info->ndcb2); + pr_debug("Command3 0x%x\n", info->ndcb3); + nand_writel(info, NDCB0, info->ndcb0); nand_writel(info, NDCB0, info->ndcb1); nand_writel(info, NDCB0, info->ndcb2); @@ -1154,6 +1160,7 @@ static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this) int ret; if (info->need_wait) { + pr_debug("Waiting for device to be ready\n"); ret = wait_for_completion_timeout(&info->dev_ready, CHIP_DELAY_TIMEOUT); info->need_wait = 0; @@ -1161,6 +1168,7 @@ static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this) dev_err(&info->pdev->dev, "Ready time out!!!\n"); return NAND_STATUS_FAIL; } + pr_debug("Device is ready\n"); } /* pxa3xx_nand_send_command has waited for command complete */ @@ -1468,6 +1476,10 @@ KEEP_CONFIG: if (nand_scan_ident(mtd, 1, def)) return -ENODEV; + pr_info("Control register dump 0x%x\n", info->reg_ndcr); + pr_info("Timing 0 register dump 0x%x\n", info->ndtr0cs0); + pr_info("Timing 1 register dump 0x%x\n", info->ndtr1cs0); + if (pdata->flash_bbt) { /* * We'll use a bad block table stored in-flash and don't