| Message ID | 1538490605-26653-1-git-send-email-dinguyen@kernel.org |
|---|---|
| State | New |
| Headers | show |
| Series | [GIT,PULL] SoCFPGA DTS updates for v4.20, part 3 | expand |
On Tue, Oct 2, 2018 at 4:30 PM Dinh Nguyen <dinguyen@kernel.org> wrote: > Dinh Nguyen (1): > arm64: dts: stratix10: add ethernet aliases This one doesn't look quite right: you are adding the aliases in the .dtsi files, which might be shared by multiple .dts files. There is no guarantee that each board uses all three ethernet ports in the chip, even when all boards we support in the kernel do. Can you have a look at why those are not in the .dts file? Arnd
Hi Arnd, On 10/04/2018 09:12 AM, Arnd Bergmann wrote: > On Tue, Oct 2, 2018 at 4:30 PM Dinh Nguyen <dinguyen@kernel.org> wrote: > >> Dinh Nguyen (1): >> arm64: dts: stratix10: add ethernet aliases > > This one doesn't look quite right: you are adding the aliases in the .dtsi > files, which might be shared by multiple .dts files. There is no guarantee > that each board uses all three ethernet ports in the chip, even when all > boards we support in the kernel do. > I kinda thought it would make sense to have all the ethernet aliases in the dtsi file because even if different boards do not use all the ethernets ports, the unused ethernet ports would be left disabled from the dtsi file. But then some boards may just use gmac1 or gmac2 instead of gmac0. So yes, I'll move the aliases to the specific board file. Thanks, Dinh
Hi Arnd, Kevin, and Olof: Please pull in these additional patches for v4.20. Thanks, Dinh The following changes since commit 20373e0cb8f7d540ae082a8026f5ae7c27cc6cb3: ARM: dts: socfpga: add timer resets for SoCFPGA platform (2018-09-17 10:11:28 -0500) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git tags/socfpga_updates_for_v4.20_part3 for you to fetch changes up to 725fc0551c9d124abd032273f49963d7f3cc4fa3: arm64: dts: stratix10: add ethernet aliases (2018-09-28 14:33:03 -0500) ---------------------------------------------------------------- SoCFPGA DTS updates for v4.20, part 3 - Add ethernet aliases for Arria10 and Stratix10 - Correct system manager register size for Stratix10 - Correct SDRAM node address for Arria10 ---------------------------------------------------------------- Dinh Nguyen (1): arm64: dts: stratix10: add ethernet aliases Steffen Trumtrar (1): ARM: dts: socfpga: arria10: add aliases for ethernet Thor Thayer (2): ARM: dts: socfpga: Fix SDRAM node address for Arria10 arm64: dts: stratix10: Correct System Manager register size arch/arm/boot/dts/socfpga_arria10.dtsi | 9 ++++++++- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8 +++++++- 2 files changed, 15 insertions(+), 2 deletions(-)