| Message ID | 1472478597-6731-2-git-send-email-Anson.Huang@nxp.com |
|---|---|
| State | New |
| Headers | show
Return-Path: <linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org> X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2001:1868:205::9]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3sN1LQ0qrBz9s9x for <incoming-imx@patchwork.ozlabs.org>; Mon, 29 Aug 2016 16:03:58 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1beFeJ-0001ZD-R1; Mon, 29 Aug 2016 06:02:23 +0000 Received: from mail-sn1nam01on0076.outbound.protection.outlook.com ([104.47.32.76] helo=NAM01-SN1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1beFdw-0001KC-Aq for linux-arm-kernel@lists.infradead.org; Mon, 29 Aug 2016 06:02:02 +0000 Received: from BY2PR03CA076.namprd03.prod.outlook.com (10.141.249.49) by BY2PR0301MB2008.namprd03.prod.outlook.com (10.163.196.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA_P384) id 15.1.587.9; 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Sun, 28 Aug 2016 23:01:34 -0700 From: Anson Huang <Anson.Huang@nxp.com> To: <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH V2 2/2] ARM: imx: enable WAIT mode hardware workaround for imx6sx Date: Mon, 29 Aug 2016 21:49:57 +0800 Message-ID: <1472478597-6731-2-git-send-email-Anson.Huang@nxp.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1472478597-6731-1-git-send-email-Anson.Huang@nxp.com> References: <1472478597-6731-1-git-send-email-Anson.Huang@nxp.com> X-EOPAttributedMessage: 0 X-Matching-Connectors: 131169240977014452; (91ab9b29-cfa4-454e-5278-08d120cd25b8); () X-Forefront-Antispam-Report: CIP:192.88.168.50; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(7916002)(2980300002)(1109001)(1110001)(339900001)(199003)(189002)(48376002)(2906002)(86362001)(189998001)(92566002)(586003)(4326007)(50466002)(8936002)(7846002)(8666005)(356003)(68736007)(305945005)(36756003)(5001770100001)(97736004)(77096005)(11100500001)(104016004)(5660300001)(626004)(19580395003)(76176999)(47776003)(8676002)(105606002)(5003940100001)(19580405001)(229853001)(85426001)(50226002)(87936001)(2950100001)(81156014)(81166006)(50986999)(106466001)(7059030)(32563001)(2101003); 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org |
diff --git a/arch/arm/mach-imx/cpuidle-imx6sx.c b/arch/arm/mach-imx/cpuidle-imx6sx.c index 3c6672b..261aaa4 100644 --- a/arch/arm/mach-imx/cpuidle-imx6sx.c +++ b/arch/arm/mach-imx/cpuidle-imx6sx.c @@ -90,6 +90,7 @@ static struct cpuidle_driver imx6sx_cpuidle_driver = { int __init imx6sx_cpuidle_init(void) { + imx6_set_int_mem_clk_lpm(true); imx6_enable_rbc(false); /* * set ARM power up/down timing to the fastest,
Need to enable INT_MEM_CLK_LPM bit in CCM_CGPR for WAIT mode, without this bit set, if there is pending interrupt during ARM platform entering WAIT mode without power gating, cache data will be corrupted, this is a hardware workaround for WAIT mode and must be enabled. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> --- changes since V1: function name is changed in 1/2 patch, change it accordingly. arch/arm/mach-imx/cpuidle-imx6sx.c | 1 + 1 file changed, 1 insertion(+)