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[73.225.163.254]) by smtp.gmail.com with ESMTPSA id fl1sm34039523pab.43.2016.06.12.22.55.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 12 Jun 2016 22:55:47 -0700 (PDT) From: Andrey Smirnov To: linux-arm-kernel@lists.infradead.org Subject: [RESEND PATCH 2/3] i.MX: system.c: Remove redundant errata 752271 code Date: Sun, 12 Jun 2016 22:55:28 -0700 Message-Id: <1465797329-22537-2-git-send-email-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1465797329-22537-1-git-send-email-andrew.smirnov@gmail.com> References: <1465797329-22537-1-git-send-email-andrew.smirnov@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160612_225609_053533_F673333B X-CRM114-Status: GOOD ( 12.21 ) X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [2607:f8b0:400e:c00:0:0:0:241 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (andrew.smirnov[at]gmail.com) -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Shawn Guo , Russell King , linux-kernel@vger.kernel.org, Sascha Hauer MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org Applying a fix for ARM errata 752271 would already be taken care by a call to a 'fixup' hook as a part of l2x0_of_init() -> __l2c_init() call chain. Moreso the code in 'fixup' function would do that based on the PL310's revsion information, whereas removed code does so based on SoC version which does not work very well on i.MX6Q+ which identifies itself as i.MX6Q, but is not affected by 752271. Signed-off-by: Andrey Smirnov --- RESEND, now with Russell King on CC list. arch/arm/mach-imx/system.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c index d9f8b0e..b153376 100644 --- a/arch/arm/mach-imx/system.c +++ b/arch/arm/mach-imx/system.c @@ -110,17 +110,6 @@ void __init imx_init_l2cache(void) /* Configure the L2 PREFETCH and POWER registers */ val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL); val |= 0x70800000; - /* - * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 - * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 - * But according to ARM PL310 errata: 752271 - * ID: 752271: Double linefill feature can cause data corruption - * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 - * Workaround: The only workaround to this erratum is to disable the - * double linefill feature. This is the default behavior. - */ - if (cpu_is_imx6q()) - val &= ~(1 << 30 | 1 << 23); writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL); }