diff mbox

[v2,2/6] imx35: define two clocks for rtc

Message ID 1434809732-8996-3-git-send-email-tremyfr@gmail.com
State New
Headers show

Commit Message

Philippe Reynes June 20, 2015, 2:15 p.m. UTC 
The imx35 don't define clocks for rtc.
This patch add two clocks, as needed
by the mxc rtc driver.

Signed-off-by: Philippe Reynes <tremyfr@gmail.com>
---
 arch/arm/mach-imx/clk-imx35.c |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

Comments

Fabio Estevam June 20, 2015, 2:43 p.m. UTC | #1 
On Sat, Jun 20, 2015 at 11:15 AM, Philippe Reynes <tremyfr@gmail.com> wrote:

> @@ -240,6 +241,9 @@ int __init mx35_clocks_init(void)
>         clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1");
>         clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2");
>         clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2");
> +       /* i.mx35 has the i.mx21 type uart */

I think you meant rtc, not uart :-)
Philippe Reynes June 20, 2015, 4:48 p.m. UTC | #2 
Hi Fabio,

On 20/06/15 16:43, Fabio Estevam wrote:
> On Sat, Jun 20, 2015 at 11:15 AM, Philippe Reynes<tremyfr@gmail.com>  wrote:
>
>> @@ -240,6 +241,9 @@ int __init mx35_clocks_init(void)
>>          clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1");
>>          clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2");
>>          clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2");
>> +       /* i.mx35 has the i.mx21 type uart */
>
> I think you meant rtc, not uart :-)

Yes, of course, sorry for this silly mistake.
I fix it in a V3.

Thanks a lot,
Philippe
diff mbox

Patch

diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index a0d2b57..8c2f507 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -51,7 +51,7 @@  static const char *std_sel[] = {"ppll", "arm"};
 static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"};
 
 enum mx35_clks {
-	ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg,
+	ckih, ckil, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg,
 	arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, esdhc_sel,
 	esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel, spdif_div_pre,
 	spdif_div_post, ssi_sel, ssi1_div_pre, ssi1_div_post, ssi2_div_pre,
@@ -89,6 +89,7 @@  int __init mx35_clocks_init(void)
 	}
 
 	clk[ckih] = imx_clk_fixed("ckih", 24000000);
+	clk[ckil] = imx_clk_fixed("ckih", 32768);
 	clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MX35_CCM_MPCTL);
 	clk[ppll] = imx_clk_pllv1("ppll", "ckih", base + MX35_CCM_PPCTL);
 
@@ -240,6 +241,9 @@  int __init mx35_clocks_init(void)
 	clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1");
 	clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2");
 	clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2");
+	/* i.mx35 has the i.mx21 type uart */
+	clk_register_clkdev(clk[ckil], "rtc", "imx21-rtc");
+	clk_register_clkdev(clk[rtc_gate], "ipg", "imx21-rtc");
 	clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
 	clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
 	clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.0");