From patchwork Fri May 22 15:29:52 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 475683 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2001:1868:205::9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 8FCDC14077A for ; Sat, 23 May 2015 01:39:16 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Yvoz5-0001T0-K9; Fri, 22 May 2015 15:35:39 +0000 Received: from mail-pa0-f48.google.com ([209.85.220.48]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YvovZ-0006KF-R0 for linux-arm-kernel@lists.infradead.org; Fri, 22 May 2015 15:32:02 +0000 Received: by padbw4 with SMTP id bw4so22452071pad.0 for ; Fri, 22 May 2015 08:31:41 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zhAXAp1ctZ+52P8oFDbIHfkzRPxF89decu7qrAJkYHs=; b=VxikVEOjk8wntG10iyhbONlWplt/YKX3ZcCh8xc34UTfLPW1czBx+TEbuHvLMT0Hs9 Y70FObv3EgtUfpxbirH2601WVLCeGhJG+WhEQryVgcnj06P9C5S0SSDfYggZ++TCVI8g trzYJJFJoOLaGPWQHdGTO/3JAVZLOFYnNFV+EcH+tZHA57IbzDW8R6LNtaP80RZztH3j O8otS2eq/FYcS3AAEbN0cmQI4RXxNchhkZMG7BDIz5GBs35X2JGwh3/DhpkM+hE3LhP8 R4H8Az2nQ8X7PIpSD70/lbSYo5R1g6Gf+UOMosiL2SSYVP0uH9jdZGqKel4Z58VR8IoC LsIQ== X-Gm-Message-State: ALoCoQn0Nj/uSm2FuxKWInI7Y1KZwe2BcjTSnSS1La2CPr+ipNr1h9Dtfw+UtnrUJeOAXOdlRH7V X-Received: by 10.70.103.177 with SMTP id fx17mr16741534pdb.11.1432308701112; Fri, 22 May 2015 08:31:41 -0700 (PDT) Received: from localhost.localdomain ([107.6.117.178]) by mx.google.com with ESMTPSA id as1sm2474485pbc.39.2015.05.22.08.31.36 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 22 May 2015 08:31:40 -0700 (PDT) From: Shawn Guo To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 05/12] ARM: imx: setup tctl register in device specific function Date: Fri, 22 May 2015 23:29:52 +0800 Message-Id: <1432308599-28643-6-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1432308599-28643-1-git-send-email-shawn.guo@linaro.org> References: <1432308599-28643-1-git-send-email-shawn.guo@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150522_083202_023334_C3E88280 X-CRM114-Status: GOOD ( 15.92 ) X-Spam-Score: -1.8 (-) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-1.8 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.48 listed in list.dnswl.org] -1.1 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [209.85.220.48 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record Cc: Shawn Guo , Daniel Lezcano , Arnd Bergmann , kernel@pengutronix.de, Shenwei Wang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org It creates a gpt device speicific data structure and adds function hook gpt_setup_tctl in there to set up gpt TCTL register. Signed-off-by: Shawn Guo Tested-by: Kevin Hilman --- arch/arm/mach-imx/time.c | 98 ++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 78 insertions(+), 20 deletions(-) diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index cf88355654dd..2fbc3022ce3f 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c @@ -92,6 +92,11 @@ struct imx_timer { int irq; struct clk *clk_per; struct clk *clk_ipg; + const struct imx_gpt_data *gpt; +}; + +struct imx_gpt_data { + void (*gpt_setup_tctl)(struct imx_timer *imxtm); }; static void __iomem *timer_base; @@ -307,13 +312,83 @@ static int __init mxc_clockevent_init(struct imx_timer *imxtm) return 0; } -static void __init _mxc_timer_init(struct imx_timer *imxtm) +static void imx1_gpt_setup_tctl(struct imx_timer *imxtm) +{ + u32 tctl_val; + + tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; + writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); +} +#define imx21_gpt_setup_tctl imx1_gpt_setup_tctl + +static void imx31_gpt_setup_tctl(struct imx_timer *imxtm) +{ + u32 tctl_val; + + tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; + if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) + tctl_val |= V2_TCTL_CLK_OSC_DIV8; + else + tctl_val |= V2_TCTL_CLK_PER; + + writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); +} + +static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm) { - uint32_t tctl_val; + u32 tctl_val; + + tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; + if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) { + tctl_val |= V2_TCTL_CLK_OSC_DIV8; + /* 24 / 8 = 3 MHz */ + writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER); + tctl_val |= V2_TCTL_24MEN; + } else { + tctl_val |= V2_TCTL_CLK_PER; + } + + writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); +} +static const struct imx_gpt_data imx1_gpt_data = { + .gpt_setup_tctl = imx1_gpt_setup_tctl, +}; + +static const struct imx_gpt_data imx21_gpt_data = { + .gpt_setup_tctl = imx21_gpt_setup_tctl, +}; + +static const struct imx_gpt_data imx31_gpt_data = { + .gpt_setup_tctl = imx31_gpt_setup_tctl, +}; + +static const struct imx_gpt_data imx6dl_gpt_data = { + .gpt_setup_tctl = imx6dl_gpt_setup_tctl, +}; + +static void __init _mxc_timer_init(struct imx_timer *imxtm) +{ /* Temporary */ timer_base = imxtm->base; + switch (imxtm->type) { + case GPT_TYPE_IMX1: + imxtm->gpt = &imx1_gpt_data; + break; + case GPT_TYPE_IMX21: + imxtm->gpt = &imx21_gpt_data; + break; + case GPT_TYPE_IMX31: + imxtm->gpt = &imx31_gpt_data; + break; + case GPT_TYPE_IMX6DL: + imxtm->gpt = &imx6dl_gpt_data; + break; + default: + BUG(); + } + if (IS_ERR(imxtm->clk_per)) { pr_err("i.MX timer: unable to get clk\n"); return; @@ -331,24 +406,7 @@ static void __init _mxc_timer_init(struct imx_timer *imxtm) writel_relaxed(0, imxtm->base + MXC_TCTL); writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */ - if (timer_is_v2()) { - tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; - if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) { - tctl_val |= V2_TCTL_CLK_OSC_DIV8; - if (cpu_is_imx6dl() || cpu_is_imx6sx()) { - /* 24 / 8 = 3 MHz */ - writel_relaxed(7 << V2_TPRER_PRE24M, - imxtm->base + MXC_TPRER); - tctl_val |= V2_TCTL_24MEN; - } - } else { - tctl_val |= V2_TCTL_CLK_PER; - } - } else { - tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; - } - - writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); + imxtm->gpt->gpt_setup_tctl(imxtm); /* init and register the timer to the framework */ mxc_clocksource_init(imxtm);