From patchwork Fri May 22 15:29:49 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 475680 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2001:1868:205::9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 2DACC1402A5 for ; Sat, 23 May 2015 01:37:36 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Yvoxa-0007gO-HP; Fri, 22 May 2015 15:34:06 +0000 Received: from mail-pa0-f43.google.com ([209.85.220.43]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YvovL-00069z-0F for linux-arm-kernel@lists.infradead.org; Fri, 22 May 2015 15:31:48 +0000 Received: by pacwv17 with SMTP id wv17so22349630pac.2 for ; Fri, 22 May 2015 08:31:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=El5ikVs6cKZu4JUMOStZ6CjVqWyEAXD0UeQI6KBSnbE=; b=PNtuQl/X8cEZB4rgqQq2WfEc0z6dD3t/E8r61zEwx4JDik8Ww7CduqMAKaf+ep0i5+ ow3/H64KHYtKW3BmtRss2fMoXvLoF2GnvDC1dfzaQUL60VtY1QYQQ0RycaR4COoCvl5W hR4M6M11c2UNsxkvGdyOGQpizjkZTKlVsEsrj2F2z30nROHvvweaRXoGLE44qZHr6AL/ Wm/2grAvSSZ6xH1H6LyzayftktFNyMukeDldOPjzm2JCyEyL3JfbUIFPdDLemu1yd2tX RCWcFlaKwfMXV4DYT6EbevCoR092k/yNVWhoV/sBSG7ftNR6CbGS8dXEBvw09Q+zoAO6 TB+g== X-Gm-Message-State: ALoCoQlWfAS7LYyXUbcikHZMs+5/gkqhEVWt5vECGCCvNyujOuwEo9gCVR95dm/gCr6ntifpRzJ/ X-Received: by 10.66.222.72 with SMTP id qk8mr16573900pac.7.1432308685614; Fri, 22 May 2015 08:31:25 -0700 (PDT) Received: from localhost.localdomain ([107.6.117.178]) by mx.google.com with ESMTPSA id as1sm2474485pbc.39.2015.05.22.08.31.21 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 22 May 2015 08:31:24 -0700 (PDT) From: Shawn Guo To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 02/12] ARM: imx: move timer resources into a structure Date: Fri, 22 May 2015 23:29:49 +0800 Message-Id: <1432308599-28643-3-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1432308599-28643-1-git-send-email-shawn.guo@linaro.org> References: <1432308599-28643-1-git-send-email-shawn.guo@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150522_083147_083255_A610C546 X-CRM114-Status: GOOD ( 18.58 ) X-Spam-Score: -1.8 (-) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-1.8 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.43 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.1 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [209.85.220.43 listed in wl.mailspike.net] Cc: Shawn Guo , Daniel Lezcano , Arnd Bergmann , kernel@pengutronix.de, Shenwei Wang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org Instead of passing around as individual argument, let's move timer resources like irq and clocks together with base address into a data structure, and pass pointer of the structure as argument to simplify the function call interface. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/time.c | 91 +++++++++++++++++++++++++++++------------------- 1 file changed, 56 insertions(+), 35 deletions(-) diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index 376d5d8ccfb8..7c131e1b2637 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -84,6 +85,13 @@ static struct clock_event_device clockevent_mxc; static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; +struct imx_timer { + void __iomem *base; + int irq; + struct clk *clk_per; + struct clk *clk_ipg; +}; + static void __iomem *timer_base; static inline void gpt_irq_disable(void) @@ -134,10 +142,10 @@ static unsigned long imx_read_current_timer(void) return readl_relaxed(sched_clock_reg); } -static int __init mxc_clocksource_init(struct clk *timer_clk) +static int __init mxc_clocksource_init(struct imx_timer *imxtm) { - unsigned int c = clk_get_rate(timer_clk); - void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN); + unsigned int c = clk_get_rate(imxtm->clk_per); + void __iomem *reg = imxtm->base + (timer_is_v2() ? V2_TCN : MX1_2_TCN); imx_delay_timer.read_current_timer = &imx_read_current_timer; imx_delay_timer.freq = c; @@ -284,49 +292,51 @@ static struct clock_event_device clockevent_mxc = { .rating = 200, }; -static int __init mxc_clockevent_init(struct clk *timer_clk) +static int __init mxc_clockevent_init(struct imx_timer *imxtm) { if (timer_is_v2()) clockevent_mxc.set_next_event = v2_set_next_event; clockevent_mxc.cpumask = cpumask_of(0); clockevents_config_and_register(&clockevent_mxc, - clk_get_rate(timer_clk), + clk_get_rate(imxtm->clk_per), 0xff, 0xfffffffe); return 0; } -static void __init _mxc_timer_init(int irq, - struct clk *clk_per, struct clk *clk_ipg) +static void __init _mxc_timer_init(struct imx_timer *imxtm) { uint32_t tctl_val; - if (IS_ERR(clk_per)) { + /* Temporary */ + timer_base = imxtm->base; + + if (IS_ERR(imxtm->clk_per)) { pr_err("i.MX timer: unable to get clk\n"); return; } - if (!IS_ERR(clk_ipg)) - clk_prepare_enable(clk_ipg); + if (!IS_ERR(imxtm->clk_ipg)) + clk_prepare_enable(imxtm->clk_ipg); - clk_prepare_enable(clk_per); + clk_prepare_enable(imxtm->clk_per); /* * Initialise to a known state (all timers off, and timing reset) */ - writel_relaxed(0, timer_base + MXC_TCTL); - writel_relaxed(0, timer_base + MXC_TPRER); /* see datasheet note */ + writel_relaxed(0, imxtm->base + MXC_TCTL); + writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */ if (timer_is_v2()) { tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; - if (clk_get_rate(clk_per) == V2_TIMER_RATE_OSC_DIV8) { + if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) { tctl_val |= V2_TCTL_CLK_OSC_DIV8; if (cpu_is_imx6dl() || cpu_is_imx6sx()) { /* 24 / 8 = 3 MHz */ writel_relaxed(7 << V2_TPRER_PRE24M, - timer_base + MXC_TPRER); + imxtm->base + MXC_TPRER); tctl_val |= V2_TCTL_24MEN; } } else { @@ -336,47 +346,58 @@ static void __init _mxc_timer_init(int irq, tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; } - writel_relaxed(tctl_val, timer_base + MXC_TCTL); + writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); /* init and register the timer to the framework */ - mxc_clocksource_init(clk_per); - mxc_clockevent_init(clk_per); + mxc_clocksource_init(imxtm); + mxc_clockevent_init(imxtm); /* Make irqs happen */ - setup_irq(irq, &mxc_timer_irq); + setup_irq(imxtm->irq, &mxc_timer_irq); } void __init mxc_timer_init(unsigned long pbase, int irq) { - struct clk *clk_per = clk_get_sys("imx-gpt.0", "per"); - struct clk *clk_ipg = clk_get_sys("imx-gpt.0", "ipg"); + struct imx_timer *imxtm; + + imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL); + BUG_ON(!imxtm); - timer_base = ioremap(pbase, SZ_4K); - BUG_ON(!timer_base); + imxtm->clk_per = clk_get_sys("imx-gpt.0", "per"); + imxtm->clk_ipg = clk_get_sys("imx-gpt.0", "ipg"); - _mxc_timer_init(irq, clk_per, clk_ipg); + imxtm->base = ioremap(pbase, SZ_4K); + BUG_ON(!imxtm->base); + + _mxc_timer_init(imxtm); } static void __init mxc_timer_init_dt(struct device_node *np) { - struct clk *clk_per, *clk_ipg; - int irq; + struct imx_timer *imxtm; + static int initialized; - if (timer_base) + /* Support one instance only */ + if (initialized) return; - timer_base = of_iomap(np, 0); - WARN_ON(!timer_base); - irq = irq_of_parse_and_map(np, 0); + imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL); + BUG_ON(!imxtm); - clk_ipg = of_clk_get_by_name(np, "ipg"); + imxtm->base = of_iomap(np, 0); + WARN_ON(!imxtm->base); + imxtm->irq = irq_of_parse_and_map(np, 0); + + imxtm->clk_ipg = of_clk_get_by_name(np, "ipg"); /* Try osc_per first, and fall back to per otherwise */ - clk_per = of_clk_get_by_name(np, "osc_per"); - if (IS_ERR(clk_per)) - clk_per = of_clk_get_by_name(np, "per"); + imxtm->clk_per = of_clk_get_by_name(np, "osc_per"); + if (IS_ERR(imxtm->clk_per)) + imxtm->clk_per = of_clk_get_by_name(np, "per"); + + _mxc_timer_init(imxtm); - _mxc_timer_init(irq, clk_per, clk_ipg); + initialized = 1; } CLOCKSOURCE_OF_DECLARE(mx1_timer, "fsl,imx1-gpt", mxc_timer_init_dt); CLOCKSOURCE_OF_DECLARE(mx25_timer, "fsl,imx25-gpt", mxc_timer_init_dt);