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[v2,11/11] ARM: dts: zynq: Add AXI clkgen for Parallella

Message ID 1406242820-20140-12-git-send-email-afaerber@suse.de
State New
Headers show

Commit Message

Andreas Färber July 24, 2014, 11 p.m. UTC 
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v2: New
 
 arch/arm/boot/dts/zynq-parallella.dts | 7 +++++++
 1 file changed, 7 insertions(+)
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Patch

diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
index 65fbd8b..d2eefad 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -57,6 +57,13 @@ 
 			};
 		};
 
+		axi_clkgen: axi-clkgen@66000000 {
+			compatible = "adi,axi-clkgen-1.00.a";
+			reg = <0x66000000 0x10000>;
+			#clock-cells = <0>;
+			clocks = <&clkc 17>;
+		};
+
 		audio_clock: audio-clock {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;