From patchwork Tue May 20 08:45:35 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 350576 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2001:1868:205::9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id EAFD114007F for ; Tue, 20 May 2014 18:54:00 +1000 (EST) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WmfjG-0005PQ-9z; Tue, 20 May 2014 08:48:58 +0000 Received: from mail-bn1lp0144.outbound.protection.outlook.com ([207.46.163.144] helo=na01-bn1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Wmfh9-0003q8-3Z for linux-arm-kernel@lists.infradead.org; Tue, 20 May 2014 08:46:48 +0000 Received: from DM2PR03CA004.namprd03.prod.outlook.com (10.141.52.152) by DM2PR03MB349.namprd03.prod.outlook.com (10.141.54.11) with Microsoft SMTP Server (TLS) id 15.0.944.11; Tue, 20 May 2014 08:46:24 +0000 Received: from BY2FFO11FD014.protection.gbl (2a01:111:f400:7c0c::106) by DM2PR03CA004.outlook.office365.com (2a01:111:e400:2414::24) with Microsoft SMTP Server (TLS) id 15.0.944.11 via Frontend Transport; Tue, 20 May 2014 08:46:24 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BY2FFO11FD014.mail.protection.outlook.com (10.1.14.76) with Microsoft SMTP Server (TLS) id 15.0.949.9 via Frontend Transport; Tue, 20 May 2014 08:46:23 +0000 Received: from dragon.ap.freescale.net ([10.192.185.75]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s4K8je57027018; Tue, 20 May 2014 01:46:20 -0700 From: Shawn Guo To: Subject: [PATCH 17/20] ARM: imx5: move init hooks into mach-imx5x.c Date: Tue, 20 May 2014 16:45:35 +0800 Message-ID: <1400575538-21136-18-git-send-email-shawn.guo@freescale.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1400575538-21136-1-git-send-email-shawn.guo@freescale.com> References: <1400575538-21136-1-git-send-email-shawn.guo@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(6009001)(189002)(199002)(99396002)(33646001)(102836001)(50466002)(68736004)(36756003)(81342001)(69596002)(21056001)(81542001)(80022001)(77096999)(50986999)(76176999)(74502001)(48376002)(74662001)(79102001)(64706001)(47776003)(31966008)(20776003)(62966002)(15202345003)(87936001)(81156002)(88136002)(575784001)(93916002)(86362001)(89996001)(6806004)(83322001)(77156001)(19580405001)(83072002)(85852003)(19580395003)(92726001)(46102001)(44976005)(77982001)(15975445006)(50226001)(87286001)(84676001)(92566001)(97736001)(4396001)(76482001); DIR:OUT; SFP:; SCL:1; SRVR:DM2PR03MB349; H:az84smr01.freescale.net; FPR:; MLV:sfv; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Forefront-PRVS: 02176E2458 Received-SPF: Fail (: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=Shawn.Guo@freescale.com; X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140520_014647_369638_825CF58B X-CRM114-Status: GOOD ( 12.94 ) X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.3.2 on bombadil.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [207.46.163.144 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record Cc: Shawn Guo , Alexander Shiyan , kernel@pengutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org These imx5 init_early[late] hooks are called only from mach-imx5x.c. Let's move them into mach-imx5x.c. While at it, replace the static mapping in imx51_ipu_mipi_setup() with dynamic mapping. Also this function and imx_src_init() do not necessarily to be called at .init_early hook, so move them into .init_machine. The mxc_iomux_v3_init() is dropped from imx51_init_early() in the moving, since it's only needed by non-DT boot. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/common.h | 4 ---- arch/arm/mach-imx/mach-imx51.c | 39 +++++++++++++++++++++++++++++++++++++ arch/arm/mach-imx/mach-imx53.c | 11 +++++++++++ arch/arm/mach-imx/mm-imx5.c | 44 ------------------------------------------ 4 files changed, 50 insertions(+), 48 deletions(-) diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 1156bf6..b480f0b 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -34,8 +34,6 @@ void imx25_init_early(void); void imx27_init_early(void); void imx31_init_early(void); void imx35_init_early(void); -void imx51_init_early(void); -void imx53_init_early(void); void mxc_init_irq(void __iomem *); void tzic_init_irq(void); void mx1_init_irq(void); @@ -50,8 +48,6 @@ void imx25_soc_init(void); void imx27_soc_init(void); void imx31_soc_init(void); void imx35_soc_init(void); -void imx51_init_late(void); -void imx53_init_late(void); void epit_timer_init(void __iomem *base, int irq); void mxc_timer_init(void __iomem *, int); void mxc_timer_init_dt(struct device_node *); diff --git a/arch/arm/mach-imx/mach-imx51.c b/arch/arm/mach-imx/mach-imx51.c index a849d43..a2027d2 100644 --- a/arch/arm/mach-imx/mach-imx51.c +++ b/arch/arm/mach-imx/mach-imx51.c @@ -10,6 +10,7 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include #include #include #include @@ -17,18 +18,56 @@ #include #include "common.h" +#include "hardware.h" #include "mx51.h" +static void __init imx51_init_early(void) +{ + mxc_set_cpu_type(MXC_CPU_MX51); +} + +/* + * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by + * the Freescale marketing division. However this did not remove the + * hardware from the chip which still needs to be configured for proper + * IPU support. + */ +#define MX51_MIPI_HSC_BASE 0x83fdc000 +static void __init imx51_ipu_mipi_setup(void) +{ + void __iomem *hsc_addr; + + hsc_addr = ioremap(MX51_MIPI_HSC_BASE, SZ_16K); + WARN_ON(!hsc_addr); + + /* setup MIPI module to legacy mode */ + __raw_writel(0xf00, hsc_addr); + + /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */ + __raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff, + hsc_addr + 0x800); + + iounmap(hsc_addr); +} + static void __init imx51_dt_init(void) { struct platform_device_info devinfo = { .name = "cpufreq-cpu0", }; mxc_arch_reset_init_dt(); + imx51_ipu_mipi_setup(); + imx_src_init(); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); platform_device_register_full(&devinfo); } +static void __init imx51_init_late(void) +{ + mx51_neon_fixup(); + imx51_pm_init(); +} + static const char *imx51_dt_board_compat[] __initconst = { "fsl,imx51", NULL diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c index 9a066af..40005b8 100644 --- a/arch/arm/mach-imx/mach-imx53.c +++ b/arch/arm/mach-imx/mach-imx53.c @@ -24,6 +24,12 @@ #include "hardware.h" #include "mx53.h" +static void __init imx53_init_early(void) +{ + mxc_set_cpu_type(MXC_CPU_MX53); + imx_src_init(); +} + static void __init imx53_dt_init(void) { mxc_arch_reset_init_dt(); @@ -31,6 +37,11 @@ static void __init imx53_dt_init(void) of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } +static void __init imx53_init_late(void) +{ + imx53_pm_init(); +} + static const char *imx53_dt_board_compat[] __initconst = { "fsl,imx53", NULL diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c index 9e43e87..768fede 100644 --- a/arch/arm/mach-imx/mm-imx5.c +++ b/arch/arm/mach-imx/mm-imx5.c @@ -59,47 +59,3 @@ void __init mx53_map_io(void) { iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc)); } - -/* - * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by - * the Freescale marketing division. However this did not remove the - * hardware from the chip which still needs to be configured for proper - * IPU support. - */ -static void __init imx51_ipu_mipi_setup(void) -{ - void __iomem *hsc_addr; - hsc_addr = MX51_IO_ADDRESS(MX51_MIPI_HSC_BASE_ADDR); - - /* setup MIPI module to legacy mode */ - __raw_writel(0xf00, hsc_addr); - - /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */ - __raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff, - hsc_addr + 0x800); -} - -void __init imx51_init_early(void) -{ - imx51_ipu_mipi_setup(); - mxc_set_cpu_type(MXC_CPU_MX51); - mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); - imx_src_init(); -} - -void __init imx53_init_early(void) -{ - mxc_set_cpu_type(MXC_CPU_MX53); - imx_src_init(); -} - -void __init imx51_init_late(void) -{ - mx51_neon_fixup(); - imx51_pm_init(); -} - -void __init imx53_init_late(void) -{ - imx53_pm_init(); -}