From patchwork Thu Oct 17 03:17:14 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 284064 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from casper.infradead.org (unknown [IPv6:2001:770:15f::2]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 738172C0084 for ; Thu, 17 Oct 2013 14:17:04 +1100 (EST) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VWe4v-00073P-TH; Thu, 17 Oct 2013 03:16:50 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VWe4t-0007tn-NF; Thu, 17 Oct 2013 03:16:47 +0000 Received: from va3ehsobe001.messaging.microsoft.com ([216.32.180.11] helo=va3outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VWe4p-0007sV-Ag for linux-arm-kernel@lists.infradead.org; Thu, 17 Oct 2013 03:16:45 +0000 Received: from mail172-va3-R.bigfish.com (10.7.14.241) by VA3EHSOBE003.bigfish.com (10.7.40.23) with Microsoft SMTP Server id 14.1.225.23; Thu, 17 Oct 2013 03:16:20 +0000 Received: from mail172-va3 (localhost [127.0.0.1]) by mail172-va3-R.bigfish.com (Postfix) with ESMTP id 7FFAC42019A; Thu, 17 Oct 2013 03:16:20 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zcb8kzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz1de098h8275dh1de097hz2dh87h2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h1151h1155h) X-FB-DOMAIN-IP-MATCH: fail Received: from mail172-va3 (localhost.localdomain [127.0.0.1]) by mail172-va3 (MessageSwitch) id 1381979778251537_8466; Thu, 17 Oct 2013 03:16:18 +0000 (UTC) Received: from VA3EHSMHS028.bigfish.com (unknown [10.7.14.249]) by mail172-va3.bigfish.com (Postfix) with ESMTP id 37E9D6004A; Thu, 17 Oct 2013 03:16:18 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS028.bigfish.com (10.7.99.38) with Microsoft SMTP Server (TLS) id 14.16.227.3; Thu, 17 Oct 2013 03:16:18 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.3.158.2; Thu, 17 Oct 2013 03:16:17 +0000 Received: from S2101-09.ap.freescale.net ([10.192.185.68]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id r9H3G8sm024540; Wed, 16 Oct 2013 20:16:15 -0700 From: Shawn Guo To: Subject: [PATCH 4/4] ARM: imx: enable suspend for imx6sl Date: Thu, 17 Oct 2013 11:17:14 +0800 Message-ID: <1381979834-20998-5-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1381979834-20998-1-git-send-email-shawn.guo@linaro.org> References: <1381979834-20998-1-git-send-email-shawn.guo@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131016_231643_454316_2FB05EA8 X-CRM114-Status: GOOD ( 13.21 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [216.32.180.11 listed in list.dnswl.org] 0.7 SPF_SOFTFAIL SPF: sender does not match SPF record (softfail) -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Shawn Guo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org The imx6sl low power mode implementation inherits imx6q/dl one, and pm-imx6q.c can just work for imx6sl with some minor updates. Let's enable imx6sl suspend support by reusing pm-imx6q.c and use cpu_is_imxXX() to handle the those minor differences between imx6sl and imx6q/dl. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl.dtsi | 3 ++- arch/arm/mach-imx/Makefile | 2 ++ arch/arm/mach-imx/clk-imx6sl.c | 3 +++ arch/arm/mach-imx/mach-imx6sl.c | 3 +++ arch/arm/mach-imx/mxc.h | 5 +++++ arch/arm/mach-imx/pm-imx6q.c | 9 ++++++++- 6 files changed, 23 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 17607b3..f2f6df6 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -535,7 +535,8 @@ }; gpr: iomuxc-gpr@020e0000 { - compatible = "fsl,imx6sl-iomuxc-gpr", "syscon"; + compatible = "fsl,imx6sl-iomuxc-gpr", + "fsl,imx6q-iomuxc-gpr", "syscon"; reg = <0x020e0000 0x38>; }; diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 5383c58..bbe1f5b 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -102,6 +102,8 @@ obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o ifeq ($(CONFIG_PM),y) obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o +# i.MX6SL reuses pm-imx6q.c +obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o endif # i.MX5 based machines diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c index a5c3c5d..c0c4ef5 100644 --- a/arch/arm/mach-imx/clk-imx6sl.c +++ b/arch/arm/mach-imx/clk-imx6sl.c @@ -127,6 +127,9 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) base = of_iomap(np, 0); WARN_ON(!base); + /* Reuse imx6q pm code */ + imx6q_pm_set_ccm_base(base); + /* name reg shift width parent_names num_parents */ clks[IMX6SL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); clks[IMX6SL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c index 5c767f0..c7502f2 100644 --- a/arch/arm/mach-imx/mach-imx6sl.c +++ b/arch/arm/mach-imx/mach-imx6sl.c @@ -48,6 +48,9 @@ static void __init imx6sl_init_machine(void) of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); imx6sl_fec_init(); + imx_anatop_init(); + /* Reuse imx6q pm code */ + imx6q_pm_init(); } static void __init imx6sl_init_irq(void) diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h index 99e03ea..b08ab3a 100644 --- a/arch/arm/mach-imx/mxc.h +++ b/arch/arm/mach-imx/mxc.h @@ -153,6 +153,11 @@ extern unsigned int __mxc_cpu_type; #endif #ifndef __ASSEMBLY__ +static inline bool cpu_is_imx6sl(void) +{ + return __mxc_cpu_type == MXC_CPU_IMX6SL; +} + static inline bool cpu_is_imx6dl(void) { return __mxc_cpu_type == MXC_CPU_IMX6DL; diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c index f303b56..aecd9f8 100644 --- a/arch/arm/mach-imx/pm-imx6q.c +++ b/arch/arm/mach-imx/pm-imx6q.c @@ -144,6 +144,12 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) val |= 0x3 << BP_CLPCR_STBY_COUNT; val |= BM_CLPCR_VSTBY; val |= BM_CLPCR_SBYOS; + if (cpu_is_imx6sl()) { + val |= BM_CLPCR_BYPASS_PMIC_READY; + val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; + } else { + val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; + } break; default: return -EINVAL; @@ -181,7 +187,8 @@ static int imx6q_pm_enter(suspend_state_t state) imx_set_cpu_jump(0, v7_cpu_resume); /* Zzz ... */ cpu_suspend(0, imx6q_suspend_finish); - imx_smp_prepare(); + if (cpu_is_imx6q() || cpu_is_imx6dl()) + imx_smp_prepare(); imx_anatop_post_resume(); imx_gpc_post_resume(); imx6q_enable_rbc(false);