From patchwork Wed Sep 25 08:30:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 277744 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from casper.infradead.org (unknown [IPv6:2001:770:15f::2]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8DC652C009E for ; Wed, 25 Sep 2013 18:30:53 +1000 (EST) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VOkTs-0000PR-Bx; Wed, 25 Sep 2013 08:29:56 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VOkTg-0008KW-MZ; Wed, 25 Sep 2013 08:29:44 +0000 Received: from tx2ehsobe002.messaging.microsoft.com ([65.55.88.12] helo=tx2outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VOkTL-0008HF-20 for linux-arm-kernel@lists.infradead.org; Wed, 25 Sep 2013 08:29:25 +0000 Received: from mail13-tx2-R.bigfish.com (10.9.14.235) by TX2EHSOBE001.bigfish.com (10.9.40.21) with Microsoft SMTP Server id 14.1.225.22; Wed, 25 Sep 2013 08:29:01 +0000 Received: from mail13-tx2 (localhost [127.0.0.1]) by mail13-tx2-R.bigfish.com (Postfix) with ESMTP id C1FFC1C00F9; Wed, 25 Sep 2013 08:29:01 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz1de098h1de097h8275dhz2dh87h2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h1151h1155h) X-FB-DOMAIN-IP-MATCH: fail Received: from mail13-tx2 (localhost.localdomain [127.0.0.1]) by mail13-tx2 (MessageSwitch) id 1380097739967068_535; Wed, 25 Sep 2013 08:28:59 +0000 (UTC) Received: from TX2EHSMHS042.bigfish.com (unknown [10.9.14.239]) by mail13-tx2.bigfish.com (Postfix) with ESMTP id E6F28460041; Wed, 25 Sep 2013 08:28:59 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by TX2EHSMHS042.bigfish.com (10.9.99.142) with Microsoft SMTP Server (TLS) id 14.16.227.3; Wed, 25 Sep 2013 08:28:59 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.3.158.2; Wed, 25 Sep 2013 08:28:59 +0000 Received: from S2101-09.ap.freescale.net ([10.192.185.61]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id r8P8SpJi003253; Wed, 25 Sep 2013 01:28:57 -0700 From: Shawn Guo To: Subject: [PATCH 3/5] ARM: imx: add a common function to initialize revision from anatop Date: Wed, 25 Sep 2013 16:30:21 +0800 Message-ID: <1380097823-29027-4-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1380097823-29027-1-git-send-email-shawn.guo@linaro.org> References: <1380097823-29027-1-git-send-email-shawn.guo@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130925_042923_289008_7D526D75 X-CRM114-Status: GOOD ( 13.64 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [65.55.88.12 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Shawn Guo , kernel@pengutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org The patch creates a common function imx_init_revision_from_anatop() by merging imx6q_init_revision() and imx_anatop_get_digprog(), so that any SoC that encodes revision info in anatop can use it to initialize revision. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/anatop.c | 27 +++++++++++++++++++++------ arch/arm/mach-imx/common.h | 2 +- arch/arm/mach-imx/mach-imx6q.c | 25 +------------------------ 3 files changed, 23 insertions(+), 31 deletions(-) diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c index ad3b755..b2d600f 100644 --- a/arch/arm/mach-imx/anatop.c +++ b/arch/arm/mach-imx/anatop.c @@ -16,6 +16,7 @@ #include #include #include "common.h" +#include "hardware.h" #define REG_SET 0x4 #define REG_CLR 0x8 @@ -76,21 +77,35 @@ static void imx_anatop_usb_chrg_detect_disable(void) BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B); } -u32 imx_anatop_get_digprog(void) +void __init imx_init_revision_from_anatop(void) { struct device_node *np; void __iomem *anatop_base; - static u32 digprog; - - if (digprog) - return digprog; + unsigned int revision; + u32 digprog; np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); anatop_base = of_iomap(np, 0); WARN_ON(!anatop_base); digprog = readl_relaxed(anatop_base + ANADIG_DIGPROG); + iounmap(anatop_base); + + switch (digprog & 0xff) { + case 0: + revision = IMX_CHIP_REVISION_1_0; + break; + case 1: + revision = IMX_CHIP_REVISION_1_1; + break; + case 2: + revision = IMX_CHIP_REVISION_1_2; + break; + default: + revision = IMX_CHIP_REVISION_UNKNOWN; + } - return digprog; + mxc_set_cpu_type(digprog >> 16 & 0xff); + imx_set_soc_revision(revision); } void __init imx_anatop_init(void) diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 64b2b9f..282af93 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -82,6 +82,7 @@ extern void imx_set_aips(void __iomem *); extern int mxc_device_init(void); void imx_set_soc_revision(unsigned int rev); unsigned int imx_get_soc_revision(void); +void imx_init_revision_from_anatop(void); enum mxc_cpu_pwr_mode { WAIT_CLOCKED, /* wfi only */ @@ -138,7 +139,6 @@ extern void imx_gpc_restore_all(void); extern void imx_anatop_init(void); extern void imx_anatop_pre_suspend(void); extern void imx_anatop_post_resume(void); -extern u32 imx_anatop_get_digprog(void); extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); extern void imx6q_set_chicken_bit(void); diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 2efdbce..ea01ac3 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -40,29 +40,6 @@ #include "cpuidle.h" #include "hardware.h" -static void __init imx6q_init_revision(void) -{ - u32 rev = imx_anatop_get_digprog(); - u32 chip_revision; - - switch (rev & 0xff) { - case 0: - chip_revision = IMX_CHIP_REVISION_1_0; - break; - case 1: - chip_revision = IMX_CHIP_REVISION_1_1; - break; - case 2: - chip_revision = IMX_CHIP_REVISION_1_2; - break; - default: - chip_revision = IMX_CHIP_REVISION_UNKNOWN; - } - - mxc_set_cpu_type(rev >> 16 & 0xff); - imx_set_soc_revision(chip_revision); -} - static void imx6q_restart(enum reboot_mode mode, const char *cmd) { struct device_node *np; @@ -276,7 +253,7 @@ static void __init imx6q_map_io(void) static void __init imx6q_init_irq(void) { - imx6q_init_revision(); + imx_init_revision_from_anatop(); imx_init_l2cache(); imx_src_init(); imx_gpc_init();