From patchwork Fri Jun 21 21:22:00 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 253316 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from casper.infradead.org (casper.infradead.org [IPv6:2001:770:15f::2]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A0F792C03E1 for ; Sat, 22 Jun 2013 07:22:53 +1000 (EST) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Uq8n6-0007sE-LB; Fri, 21 Jun 2013 21:22:45 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Uq8n3-0005rv-4a; Fri, 21 Jun 2013 21:22:41 +0000 Received: from mail-yh0-x22a.google.com ([2607:f8b0:4002:c01::22a]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Uq8n0-0005qr-AC for linux-arm-kernel@lists.infradead.org; Fri, 21 Jun 2013 21:22:39 +0000 Received: by mail-yh0-f42.google.com with SMTP id c41so3472644yho.29 for ; Fri, 21 Jun 2013 14:22:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=b+d3StLuRWQpZzz7gWpEANJXOs8KGnjZy/PYXUl8Gk0=; b=vN+QmA7EWKcRtFNp2oN5VbwG3U8uXbNZ8C+3Wz45b+wn319r6qIhszKzLFeSWlmZ2o SaUAh2cYCDmn46P2mPjFxxzhNCntRX1zlWiT2DvVfo/Xv6esYIqcGJd7yjJ5LhKqlsA1 5Kt011/3REiOuh83WlkMCzjxBMgQglLMHJ58WexfPiResfuXYtq9OAOha7f5r8wr6cFB stqdfEuhbX0nL2MDF6ko3PpbGVWgLolwBun6i5nWA+G9vH/BI3uhuX26YsW+r60EWWbc jNPC4zyxu5TwPsvkS8VS1DI3Q59Bttzj+044S0JXC2yEv6WdLaygvqASKyub8DKo18Yg fM/Q== X-Received: by 10.236.203.232 with SMTP id f68mr8385730yho.191.1371849736343; Fri, 21 Jun 2013 14:22:16 -0700 (PDT) Received: from localhost.localdomain ([189.101.181.91]) by mx.google.com with ESMTPSA id o32sm11224798yhi.5.2013.06.21.14.22.14 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 21 Jun 2013 14:22:15 -0700 (PDT) From: Fabio Estevam To: shawn.guo@linaro.org Subject: [PATCH 2/2] ARM: dts: mx28: Fix sgtl5000 codec probe Date: Fri, 21 Jun 2013 18:22:00 -0300 Message-Id: <1371849720-14506-2-git-send-email-festevam@gmail.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1371849720-14506-1-git-send-email-festevam@gmail.com> References: <1371849720-14506-1-git-send-email-festevam@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130621_172238_442360_892EB854 X-CRM114-Status: GOOD ( 15.26 ) X-Spam-Score: -2.0 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (festevam[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: marex@denx.de, Fabio Estevam , mturquette@linaro.org, linux-arm-kernel@lists.infradead.org, lauri.hintsala@bluegiga.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org From: Fabio Estevam Since commit 9e13f345887 (ASoC: sgtl5000: Let the codec acquire its clock)it is necessary to pass a codec clock to the sgtl5000 driver. On some boards the sgtl5000 codec is driven via SAIF MCLK signal, so enable it early in machine code to allow the I2C codec access to succeed. Since the saif mclk cannot be passed as a real clock within the clock framework, let's pass a dummy one to the codec driver. Signed-off-by: Fabio Estevam --- Tested on a mx28evk board running linux-next 20130621 arch/arm/boot/dts/imx28-apx4devkit.dts | 2 +- arch/arm/boot/dts/imx28-evk.dts | 2 +- arch/arm/boot/dts/imx28-m28evk.dts | 2 +- arch/arm/mach-mxs/mach-mxs.c | 41 ++++++++++++++++++++++++++++++++++ 4 files changed, 44 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts index 43bf3c7..f26bf2f 100644 --- a/arch/arm/boot/dts/imx28-apx4devkit.dts +++ b/arch/arm/boot/dts/imx28-apx4devkit.dts @@ -147,7 +147,7 @@ reg = <0x0a>; VDDA-supply = <®_3p3v>; VDDIO-supply = <®_3p3v>; - + clocks = <&clks 65>; }; pcf8563: rtc@51 { diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 3637bf3..28f20b6 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -193,7 +193,7 @@ reg = <0x0a>; VDDA-supply = <®_3p3v>; VDDIO-supply = <®_3p3v>; - + clocks = <&clks 65>; }; at24@51 { diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts index 880df2f..a09c5bf 100644 --- a/arch/arm/boot/dts/imx28-m28evk.dts +++ b/arch/arm/boot/dts/imx28-m28evk.dts @@ -184,7 +184,7 @@ reg = <0x0a>; VDDA-supply = <®_3p3v>; VDDIO-supply = <®_3p3v>; - + clocks = <&clks 65>; }; eeprom: eeprom@51 { diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index 6298adb..57ab042 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -59,6 +60,8 @@ #define MXS_CLR_ADDR 0x8 #define MXS_TOG_ADDR 0xc +#define SAIF0 0x100 + static u32 chipid; static u32 socid; @@ -264,11 +267,46 @@ static inline void enable_clk_enet_out(void) clk_prepare_enable(clk); } +static void __init mxs_enable_mclk(void) +{ + struct device_node *np; + void __iomem *clkctrl_base, *saif_base; + + np = of_find_compatible_node(NULL, NULL, "fsl,clkctrl"); + clkctrl_base = of_iomap(np, 0); + + if (!clkctrl_base) + return; + + /* + * DIV_FRAC_EN, MCLK frequency = 44.1KHz * 512 = 22.5792MHz + * This initial MCLK frequency is just to allow I2C access to the + * SGLT5000 codec to work + */ + writel(0x10c0b, clkctrl_base + SAIF0); + + iounmap(clkctrl_base); + of_node_put(np); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx28-saif"); + saif_base = of_iomap(np, 0); + + if (!saif_base) + return; + + stmp_reset_block(saif_base); + writel(1, saif_base + STMP_OFFSET_REG_SET); + + iounmap(saif_base); + of_node_put(np); +} + static void __init imx28_evk_init(void) { update_fec_mac_prop(OUI_FSL); mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0); + mxs_enable_mclk(); } static void __init imx28_evk_post_init(void) @@ -293,6 +331,7 @@ static void __init apx4devkit_init(void) if (IS_BUILTIN(CONFIG_PHYLIB)) phy_register_fixup_for_uid(PHY_ID_KSZ8051, MICREL_PHY_ID_MASK, apx4devkit_phy_fixup); + mxs_enable_mclk(); } #define ENET0_MDC__GPIO_4_0 MXS_GPIO_NR(4, 0) @@ -483,6 +522,8 @@ static void __init mxs_machine_init(void) of_machine_is_compatible("crystalfontz,cfa10055") || of_machine_is_compatible("crystalfontz,cfa10057")) crystalfontz_init(); + else if (of_machine_is_compatible("denx,m28evk")) + mxs_enable_mclk(); of_platform_populate(NULL, of_default_bus_match_table, mxs_auxdata_lookup, parent);