From patchwork Wed Mar 20 17:39:39 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 229244 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B5AFA2C0091 for ; Wed, 20 Mar 2013 15:43:05 +1100 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UIAoi-0005jn-PH; Wed, 20 Mar 2013 04:40:00 +0000 Received: from mail-db8lp0185.outbound.messaging.microsoft.com ([213.199.154.185] helo=db8outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UIAoe-0005hR-8U for linux-arm-kernel@lists.infradead.org; Wed, 20 Mar 2013 04:39:57 +0000 Received: from mail96-db8-R.bigfish.com (10.174.8.242) by DB8EHSOBE038.bigfish.com (10.174.4.101) with Microsoft SMTP Server id 14.1.225.23; Wed, 20 Mar 2013 04:39:46 +0000 Received: from mail96-db8 (localhost [127.0.0.1]) by mail96-db8-R.bigfish.com (Postfix) with ESMTP id 3ED63CC0156; Wed, 20 Mar 2013 04:39:46 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zzzz1f42h1ee6h1de0h1202h1e76h1d1ah1d2ah1082kzz8275bhz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1155h) Received: from mail96-db8 (localhost.localdomain [127.0.0.1]) by mail96-db8 (MessageSwitch) id 1363754384245894_711; Wed, 20 Mar 2013 04:39:44 +0000 (UTC) Received: from DB8EHSMHS031.bigfish.com (unknown [10.174.8.243]) by mail96-db8.bigfish.com (Postfix) with ESMTP id 2ED84B80240; Wed, 20 Mar 2013 04:39:44 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB8EHSMHS031.bigfish.com (10.174.4.41) with Microsoft SMTP Server (TLS) id 14.1.225.23; Wed, 20 Mar 2013 04:39:44 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.2.328.11; Wed, 20 Mar 2013 04:39:42 +0000 Received: from ubuntu.ap.freescale.net (ubuntu-010192242118.ap.freescale.net [10.192.242.118]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id r2K4daPn007232; Tue, 19 Mar 2013 21:39:40 -0700 From: Anson Huang To: , Subject: [PATCH 2/3] ARM: imx: enable periphery well bias for suspend Date: Wed, 20 Mar 2013 13:39:39 -0400 Message-ID: <1363801180-8284-2-git-send-email-b20788@freescale.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1363801180-8284-1-git-send-email-b20788@freescale.com> References: <1363801180-8284-1-git-send-email-b20788@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130320_003956_554703_020601D2 X-CRM114-Status: GOOD ( 10.33 ) X-Spam-Score: 1.3 (+) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (1.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [213.199.154.185 listed in list.dnswl.org] 3.2 DATE_IN_FUTURE_12_24 Date: is 12 to 24 hours after Received: date -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: shawn.guo@linaro.org, linux@arm.linux.org.uk, kernel@pengutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org enable periphery charge pump for well biasing at suspend to reduce periphery leakage. Signed-off-by: Anson Huang --- arch/arm/mach-imx/clk-imx6q.c | 22 +++++++++++++++++++++- arch/arm/mach-imx/common.h | 4 ++-- arch/arm/mach-imx/pm-imx6q.c | 4 +++- 3 files changed, 26 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 2f9ff93..b365efc 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011-2013 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public @@ -23,6 +23,9 @@ #include "clk.h" #include "common.h" +#define CCR 0x0 +#define BM_CCR_WB_COUNT (0x7 << 16) + #define CCGR0 0x68 #define CCGR1 0x6c #define CCGR2 0x70 @@ -67,6 +70,23 @@ void imx6q_set_chicken_bit(void) writel_relaxed(val, ccm_base + CGPR); } +void imx6q_set_wb(bool enable) +{ + u32 val; + + /* configurate well bias enable bit */ + val = readl_relaxed(ccm_base + CLPCR); + val &= ~BM_CLPCR_WB_PER_AT_LPM; + val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0; + writel_relaxed(val, ccm_base + CLPCR); + + /* configurate well bias count */ + val = readl_relaxed(ccm_base + CCR); + val &= ~BM_CCR_WB_COUNT; + val |= enable ? BM_CCR_WB_COUNT : 0; + writel_relaxed(val, ccm_base + CCR); +} + int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) { u32 val = readl_relaxed(ccm_base + CLPCR); diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 004c2b3..b9125cf 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -134,7 +134,7 @@ extern void imx_anatop_pre_suspend(void); extern void imx_anatop_post_resume(void); extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); extern void imx6q_set_chicken_bit(void); - +extern void imx6q_set_wb(bool enable); extern void imx_cpu_die(unsigned int cpu); extern int imx_cpu_kill(unsigned int cpu); diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c index 05b26cd..57ca274 100644 --- a/arch/arm/mach-imx/pm-imx6q.c +++ b/arch/arm/mach-imx/pm-imx6q.c @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011-2013 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public @@ -36,8 +36,10 @@ static int imx6q_pm_enter(suspend_state_t state) imx_gpc_pre_suspend(); imx_anatop_pre_suspend(); imx_set_cpu_jump(0, v7_cpu_resume); + imx6q_set_wb(true); /* Zzz ... */ cpu_suspend(0, imx6q_suspend_finish); + imx6q_set_wb(false); imx_smp_prepare(); imx_anatop_post_resume(); imx_gpc_post_resume();