From patchwork Fri Feb 1 17:45:57 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: dinguyen@altera.com X-Patchwork-Id: 217553 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id BCAC32C0292 for ; Sat, 2 Feb 2013 04:49:36 +1100 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1U1Kh6-0004RR-3p; Fri, 01 Feb 2013 17:46:32 +0000 Received: from tx2ehsobe001.messaging.microsoft.com ([65.55.88.11] helo=tx2outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1U1KgT-0004Ca-81 for linux-arm-kernel@lists.infradead.org; Fri, 01 Feb 2013 17:45:55 +0000 Received: from mail179-tx2-R.bigfish.com (10.9.14.248) by TX2EHSOBE001.bigfish.com (10.9.40.21) with Microsoft SMTP Server id 14.1.225.23; Fri, 1 Feb 2013 17:45:50 +0000 Received: from mail179-tx2 (localhost [127.0.0.1]) by mail179-tx2-R.bigfish.com (Postfix) with ESMTP id ADAD1140273; Fri, 1 Feb 2013 17:45:50 +0000 (UTC) X-Forefront-Antispam-Report: CIP:66.35.236.232; KIP:(null); UIP:(null); IPV:NLI; H:SJ-ITEXEDGE02.altera.priv.altera.com; RD:none; EFVD:NLI X-SpamScore: -3 X-BigFish: VS-3(zz103dKzz1ee6h1de0h1202h1e76h1d1ah1d2ahzz8275ch8275bhz2fh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14ddh1504h1537h162dh1631h1758h1898h18e1h1946h1155h) Received-SPF: pass (mail179-tx2: domain of altera.com designates 66.35.236.232 as permitted sender) client-ip=66.35.236.232; envelope-from=dinguyen@altera.com; helo=SJ-ITEXEDGE02.altera.priv.altera.com ; v.altera.com ; Received: from mail179-tx2 (localhost.localdomain [127.0.0.1]) by mail179-tx2 (MessageSwitch) id 1359740748143002_2643; Fri, 1 Feb 2013 17:45:48 +0000 (UTC) Received: from TX2EHSMHS028.bigfish.com (unknown [10.9.14.253]) by mail179-tx2.bigfish.com (Postfix) with ESMTP id 094ED240045; Fri, 1 Feb 2013 17:45:48 +0000 (UTC) Received: from SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) by TX2EHSMHS028.bigfish.com (10.9.99.128) with Microsoft SMTP Server (TLS) id 14.1.225.23; Fri, 1 Feb 2013 17:45:46 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) with Microsoft SMTP Server id 8.3.297.1; Fri, 1 Feb 2013 09:36:57 -0800 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.121]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id r11HjdYk013031; Fri, 1 Feb 2013 09:45:44 -0800 (PST) From: To: Subject: [PATCHv3 for soc 3/4] arm: Add v7_invalidate_l1 to cache-v7.S Date: Fri, 1 Feb 2013 11:45:57 -0600 Message-ID: <1359740758-29703-4-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1359740758-29703-1-git-send-email-dinguyen@altera.com> References: <1359740758-29703-1-git-send-email-dinguyen@altera.com> MIME-Version: 1.0 X-OriginatorOrg: altera.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130201_124553_496585_F0112445 X-CRM114-Status: GOOD ( 15.72 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [65.55.88.11 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Arnd Bergmann , Magnus Damm , Rob Herring , linux-arm-kernel@lists.infradead.org, Sascha Hauer , Olof Johansson , Thomas Gleixner , Dinh Nguyen X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org From: Dinh Nguyen mach-socfpga is another platform that needs to use v7_invalidate_l1 to bringup additional cores. There was a comment that the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S Signed-off-by: Dinh Nguyen Acked-by: Simon Horman Acked-by: Stephen Warren Reviewed-by: Pavel Machek Tested-by: Pavel Machek Tested-by: Stephen Warren Cc: Arnd Bergmann Cc: Russell King Cc: Olof Johansson Cc: Thomas Gleixner Cc: Rob Herring Cc: Sascha Hauer Cc: Magnus Damm Reviewed-by: Santosh Shilimkar --- arch/arm/mach-imx/headsmp.S | 47 ------------------------------------- arch/arm/mach-shmobile/headsmp.S | 48 -------------------------------------- arch/arm/mach-tegra/headsmp.S | 43 ---------------------------------- arch/arm/mm/cache-v7.S | 46 ++++++++++++++++++++++++++++++++++++ 4 files changed, 46 insertions(+), 138 deletions(-) diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S index 7e49deb..921fc15 100644 --- a/arch/arm/mach-imx/headsmp.S +++ b/arch/arm/mach-imx/headsmp.S @@ -17,53 +17,6 @@ .section ".text.head", "ax" -/* - * The secondary kernel init calls v7_flush_dcache_all before it enables - * the L1; however, the L1 comes out of reset in an undefined state, so - * the clean + invalidate performed by v7_flush_dcache_all causes a bunch - * of cache lines with uninitialized data and uninitialized tags to get - * written out to memory, which does really unpleasant things to the main - * processor. We fix this by performing an invalidate, rather than a - * clean + invalidate, before jumping into the kernel. - * - * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs - * to be called for both secondary cores startup and primary core resume - * procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S. - */ -ENTRY(v7_invalidate_l1) - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache - mcr p15, 2, r0, c0, c0, 0 - mrc p15, 1, r0, c0, c0, 0 - - ldr r1, =0x7fff - and r2, r1, r0, lsr #13 - - ldr r1, =0x3ff - - and r3, r1, r0, lsr #3 @ NumWays - 1 - add r2, r2, #1 @ NumSets - - and r0, r0, #0x7 - add r0, r0, #4 @ SetShift - - clz r1, r3 @ WayShift - add r4, r3, #1 @ NumWays -1: sub r2, r2, #1 @ NumSets-- - mov r3, r4 @ Temp = NumWays -2: subs r3, r3, #1 @ Temp-- - mov r5, r3, lsl r1 - mov r6, r2, lsl r0 - orr r5, r5, r6 @ Reg = (Temp<