From patchwork Tue Dec 4 14:55:12 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 203670 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D881A2C008F for ; Wed, 5 Dec 2012 01:59:14 +1100 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TftuB-0007Hs-Ld; Tue, 04 Dec 2012 14:55:27 +0000 Received: from mail-pb0-f49.google.com ([209.85.160.49]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Tftu4-0007GR-Jp for linux-arm-kernel@lists.infradead.org; Tue, 04 Dec 2012 14:55:21 +0000 Received: by mail-pb0-f49.google.com with SMTP id un15so2524484pbc.36 for ; Tue, 04 Dec 2012 06:55:18 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=Qs86a1C7fPdyGE6OWVcJo98LMrTCtXzXMyvAS9xz6ak=; b=T2qX1w7CUfYYn0n51NcRVKGl1+8IvkQIIhadxufCZl1SLYcDH9tC8bhwKn4o7u03j7 1JyTHM5dtGNI9dj/ldMyVulTabn4iRD0D/KOebeT8rmpQ8Je4amph2JzTO36kKvIhksq uTmZYiWWgBWmUpT6G7vgd5hXXtdysgUwmRna1aysQ9h286JNV/s4YJHh1jiJTXni81U8 68+XgTfGPr1SvHjew1zgS/cNfK2RdfvkKMtHAYzc16O1Liev3kV+relVFNzml6ZU5vTD hEn0GEiG9/JvgCV0x7pRaanoErAjBHeAJoT8pjb49Kf8dMcmzOtNl7nEz+3A9IEt3yJt 2FwQ== Received: by 10.66.89.138 with SMTP id bo10mr35693424pab.1.1354632918830; Tue, 04 Dec 2012 06:55:18 -0800 (PST) Received: from S2101-09.ap.freescale.net ([114.216.216.215]) by mx.google.com with ESMTPS id gu5sm1128343pbc.10.2012.12.04.06.55.15 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 04 Dec 2012 06:55:18 -0800 (PST) From: Shawn Guo To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 1/4] ARM: imx: allow timer counter to roll over Date: Tue, 4 Dec 2012 22:55:12 +0800 Message-Id: <1354632915-27134-2-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1354632915-27134-1-git-send-email-shawn.guo@linaro.org> References: <1354632915-27134-1-git-send-email-shawn.guo@linaro.org> X-Gm-Message-State: ALoCoQnaPDJcLL6go6odGbrWpjlPo+DbU01aTOzqsbU6mLzocixGYYWWoLAj4xIx+DP5QFQGZ4Fn X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121204_095520_810613_575683A9 X-CRM114-Status: UNSURE ( 9.88 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.160.49 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Sascha Hauer , Shawn Guo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org The timer is configured in free-run mode. The counter should be allowed to roll over to 0 when reaching 0xffffffff. Let's do that by always returning 0 in set_next_event. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/time.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index f017302..858098c 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c @@ -139,8 +139,7 @@ static int mx1_2_set_next_event(unsigned long evt, __raw_writel(tcmp, timer_base + MX1_2_TCMP); - return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ? - -ETIME : 0; + return 0; } static int v2_set_next_event(unsigned long evt, @@ -152,8 +151,7 @@ static int v2_set_next_event(unsigned long evt, __raw_writel(tcmp, timer_base + V2_TCMP); - return (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ? - -ETIME : 0; + return 0; } #ifdef DEBUG