From patchwork Fri Feb 3 22:35:11 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 139483 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from merlin.infradead.org (unknown [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8E7B9104792 for ; Sat, 4 Feb 2012 09:38:18 +1100 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1RtRjD-0004xY-9v; Fri, 03 Feb 2012 22:35:35 +0000 Received: from mail-tul01m020-f177.google.com ([209.85.214.177]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1RtRj1-0004vu-7M for linux-arm-kernel@lists.infradead.org; Fri, 03 Feb 2012 22:35:24 +0000 Received: by obcuz6 with SMTP id uz6so5850891obc.36 for ; Fri, 03 Feb 2012 14:35:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=b46suNMKamzTJMfTEIT+llUKtTiHLBCYHHSamo1BoH4=; b=JxaBVjB4Ilo+wobcyf7UZnBRbFcpzIYzOoYqvKkFrruZptBKlRZ+N9Nwsn7/NzbcQ1 0rZjBn0X2YR4g+S/XG7GWoeJCdKUAr9+FENPQJX+hJMsGGbrlO3dTXdee1NNBaknr1iX A+WQFwwu2lu7z6+XIszJc5wTibqX9+wjTThxE= Received: by 10.182.41.36 with SMTP id c4mr8291205obl.21.1328308522667; Fri, 03 Feb 2012 14:35:22 -0800 (PST) Received: from rob-laptop.i.smooth-stone.com ([173.226.190.126]) by mx.google.com with ESMTPS id t9sm3430939obv.8.2012.02.03.14.35.21 (version=SSLv3 cipher=OTHER); Fri, 03 Feb 2012 14:35:22 -0800 (PST) From: Rob Herring To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 3/4] ARM: imx: add irq domain support to tzic Date: Fri, 3 Feb 2012 16:35:11 -0600 Message-Id: <1328308512-22594-4-git-send-email-robherring2@gmail.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328308512-22594-1-git-send-email-robherring2@gmail.com> References: <1328308512-22594-1-git-send-email-robherring2@gmail.com> X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.214.177 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (robherring2[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit (robherring2[at]gmail.com) -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Grant Likely , Thomas Gleixner , shawn.guo@linaro.org, b-cousson@ti.com, Rob Herring X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org From: Rob Herring Add irq domain support to tzic. This is needed to enable DT. Signed-off-by: Rob Herring --- arch/arm/plat-mxc/tzic.c | 23 ++++++++++------------- 1 files changed, 10 insertions(+), 13 deletions(-) diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c index 98308ec..25c10bb 100644 --- a/arch/arm/plat-mxc/tzic.c +++ b/arch/arm/plat-mxc/tzic.c @@ -77,7 +77,7 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type) static void tzic_irq_suspend(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - int idx = gc->irq_base >> 5; + int idx = d->hwirq / 32; __raw_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx)); } @@ -85,7 +85,7 @@ static void tzic_irq_suspend(struct irq_data *d) static void tzic_irq_resume(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - int idx = gc->irq_base >> 5; + int idx = d->hwirq / 32; __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)), tzic_base + TZIC_WAKEUP0(idx)); @@ -102,18 +102,13 @@ static struct mxc_extra_irq tzic_extra_irq = { #endif }; -static __init void tzic_init_gc(unsigned int irq_start) +static __init void tzic_init_gc(struct irq_chip_generic *gc) { - struct irq_chip_generic *gc; - struct irq_chip_type *ct; - int idx = irq_start >> 5; + struct irq_chip_type *ct = gc->chip_types; + int idx = gc->hwirq_base / 32; - gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base, - handle_level_irq); - gc->private = &tzic_extra_irq; gc->wake_enabled = IRQ_MSK(32); - ct = gc->chip_types; ct->chip.irq_mask = irq_gc_mask_disable_reg; ct->chip.irq_unmask = irq_gc_unmask_enable_reg; ct->chip.irq_set_wake = irq_gc_set_wake; @@ -122,7 +117,7 @@ static __init void tzic_init_gc(unsigned int irq_start) ct->regs.disable = TZIC_ENCLEAR0(idx); ct->regs.enable = TZIC_ENSET0(idx); - irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); + return 0; } asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs) @@ -175,8 +170,10 @@ void __init tzic_init_irq(void __iomem *irqbase) /* all IRQ no FIQ Warning :: No selection */ - for (i = 0; i < TZIC_NUM_IRQS; i += 32) - tzic_init_gc(i); + irq_setup_generic_chip_domain("tzic", NULL, 1, 0, tzic_base, + handle_level_irq, TZIC_NUM_IRQS, 0, + IRQ_NOREQUEST, 0, + tzic_init_gc, &tzic_extra_irq); #ifdef CONFIG_FIQ /* Initialize FIQ */