From patchwork Wed Jan 25 15:16:12 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jean Pihet X-Patchwork-Id: 137773 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id EF2D81007D2 for ; Thu, 26 Jan 2012 02:23:53 +1100 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Rq4e6-0003LX-Ag; Wed, 25 Jan 2012 15:20:22 +0000 Received: from mail-ww0-f49.google.com ([74.125.82.49]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Rq4aq-0001rB-4P for linux-arm-kernel@lists.infradead.org; Wed, 25 Jan 2012 15:17:01 +0000 Received: by mail-ww0-f49.google.com with SMTP id ds1so2795593wgb.18 for ; Wed, 25 Jan 2012 07:16:59 -0800 (PST) Received: by 10.180.84.201 with SMTP id b9mr23829879wiz.4.1327504619825; Wed, 25 Jan 2012 07:16:59 -0800 (PST) Received: from localhost.localdomain (55.56-66-87.adsl-dyn.isp.belgacom.be. [87.66.56.55]) by mx.google.com with ESMTPS id d9sm386585wiy.2.2012.01.25.07.16.58 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 25 Jan 2012 07:16:59 -0800 (PST) From: Jean Pihet To: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, balbi@ti.com, nm@ti.com Subject: [PATCH 10/21] OMAP3+: Smartreflex: clear ERRCONFIG_VPBOUNDINTST only on a need Date: Wed, 25 Jan 2012 16:16:12 +0100 Message-Id: <1327504583-13408-11-git-send-email-j-pihet@ti.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1327504583-13408-1-git-send-email-j-pihet@ti.com> References: <1327504583-13408-1-git-send-email-j-pihet@ti.com> MIME-Version: 1.0 X-Gm-Message-State: ALoCoQlKt6ZqDDy89Kl2cx765dYNjLwzfPctvLYg/KR1W/X00HxS3XOMc8wTKYpD9SLQTN7X3Flc X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [74.125.82.49 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Kevin Hilman , Paul Walmsley , Jean Pihet X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org From: Nishanth Menon ERRCONFIG register's VPBOUNDINTST has an additional functional meaning It force clears Sr_interruptz internal signal. This can result in scenarios where VP-> SR protocol is violated where voltage processor's As interruptz is already high, VP will never clear the signal vpirqclr. Therefore during the next force update to reset to nominal voltage, VP can’t pulsed vpirqclr => PRCM HW can’t generate the tranxdone IRQ and the situation is not recoverable untill a cold reset is invoked. To prevent this situation, check if status is set before clearing the status as this needs to be done only on a need basis. Change-Id: Ic8065d7d79df143bf46877c50f5b6b19ed105a70 Reported-by: Vincent Bour Signed-off-by: Nishanth Menon Signed-off-by: Jean Pihet --- arch/arm/mach-omap2/smartreflex.c | 22 ++++++++++++++++------ 1 files changed, 16 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c index ba6ad09..6dea30d 100644 --- a/arch/arm/mach-omap2/smartreflex.c +++ b/arch/arm/mach-omap2/smartreflex.c @@ -289,6 +289,8 @@ error: static void sr_v1_disable(struct omap_sr *sr) { int timeout = 0; + int errconf_val = ERRCONFIG_MCUACCUMINTST | ERRCONFIG_MCUVALIDINTST | + ERRCONFIG_MCUBOUNDINTST; /* Enable MCUDisableAcknowledge interrupt */ sr_modify_reg(sr, ERRCONFIG_V1, @@ -297,13 +299,13 @@ static void sr_v1_disable(struct omap_sr *sr) /* SRCONFIG - disable SR */ sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0); - /* Disable all other SR interrupts and clear the status */ + /* Disable all other SR interrupts and clear the status as needed */ + if (sr_read_reg(sr, ERRCONFIG_V1) & ERRCONFIG_VPBOUNDINTST_V1) + errconf_val |= ERRCONFIG_VPBOUNDINTST_V1; sr_modify_reg(sr, ERRCONFIG_V1, (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN | ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_VPBOUNDINTEN_V1), - (ERRCONFIG_MCUACCUMINTST | ERRCONFIG_MCUVALIDINTST | - ERRCONFIG_MCUBOUNDINTST | - ERRCONFIG_VPBOUNDINTST_V1)); + errconf_val); /* * Wait for SR to be disabled. @@ -332,9 +334,17 @@ static void sr_v2_disable(struct omap_sr *sr) /* SRCONFIG - disable SR */ sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0); - /* Disable all other SR interrupts and clear the status */ - sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2, + /* + * Disable all other SR interrupts and clear the status + * write to status register ONLY on need basis - only if status + * is set. + */ + if (sr_read_reg(sr, ERRCONFIG_V2) & ERRCONFIG_VPBOUNDINTST_V2) + sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2, ERRCONFIG_VPBOUNDINTST_V2); + else + sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2, + 0x0); sr_write_reg(sr, IRQENABLE_CLR, (IRQENABLE_MCUACCUMINT | IRQENABLE_MCUVALIDINT | IRQENABLE_MCUBOUNDSINT));