From patchwork Thu Nov 10 08:39:32 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 124820 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 9F8BEB6F62 for ; Thu, 10 Nov 2011 19:39:16 +1100 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1ROQ7p-0008TP-CI; Thu, 10 Nov 2011 08:36:45 +0000 Received: from mail-iy0-f177.google.com ([209.85.210.177]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1ROQ7k-0008LV-Th for linux-arm-kernel@lists.infradead.org; Thu, 10 Nov 2011 08:36:41 +0000 Received: by mail-iy0-f177.google.com with SMTP id p10so3315871iap.36 for ; Thu, 10 Nov 2011 00:36:40 -0800 (PST) Received: by 10.50.169.1 with SMTP id aa1mr6895832igc.9.1320914200736; Thu, 10 Nov 2011 00:36:40 -0800 (PST) Received: from localhost.localdomain ([117.80.112.86]) by mx.google.com with ESMTPS id a6sm5848353igc.3.2011.11.10.00.36.33 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 10 Nov 2011 00:36:39 -0800 (PST) From: Shawn Guo To: Sascha Hauer Subject: [PATCH 4/4] arm/imx: fix imx6q mmc error when mounting rootfs Date: Thu, 10 Nov 2011 16:39:32 +0800 Message-Id: <1320914372-4416-5-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1320914372-4416-1-git-send-email-shawn.guo@linaro.org> References: <1320914372-4416-1-git-send-email-shawn.guo@linaro.org> X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.210.177 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Shawn Guo , Chris Ball , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org The following error is seen in some case when mounting rootfs from SD/MMC cards. Waiting for root device /dev/mmcblk0p1... mmc1: host does not support reading read-only switch. assuming write-enable. mmc1: new high speed SDHC card at address b368 mmcblk0: mmc1:b368 SDC 3.74 GiB mmcblk0: p1 mmc1: Timeout waiting for hardware interrupt. mmcblk0: error -110 transferring data, sector 3678224, nr 40, cmd response 0x900, card status 0xc00 end_request: I/O error, dev mmcblk0, sector 3678225 Buffer I/O error on device mmcblk0p1, logical block 458754 lost page write due to I/O error on mmcblk0p1 This patch fixes the problem by lowering the usdhc clock and correcting watermark configuration. Signed-off-by: Shawn Guo Cc: Chris Ball Cc: Sascha Hauer Tested-by: Dirk Behme --- arch/arm/mach-imx/clock-imx6q.c | 17 ++++++++++++++++- drivers/mmc/host/sdhci-esdhc-imx.c | 8 ++++++++ 2 files changed, 24 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c index e0b926d..613a1b9 100644 --- a/arch/arm/mach-imx/clock-imx6q.c +++ b/arch/arm/mach-imx/clock-imx6q.c @@ -1139,7 +1139,7 @@ static int _clk_set_rate(struct clk *clk, unsigned long rate) return -EINVAL; max_div = ((d->bm_pred >> d->bp_pred) + 1) * - ((d->bm_pred >> d->bp_pred) + 1); + ((d->bm_podf >> d->bp_podf) + 1); div = parent_rate / rate; if (div == 0) @@ -2002,6 +2002,21 @@ int __init mx6q_clocks_init(void) clk_set_rate(&asrc_serial_clk, 1500000); clk_set_rate(&enfc_clk, 11000000); + /* + * Before pinctrl API is available, we have to rely on the pad + * configuration set up by bootloader. For usdhc example here, + * u-boot sets up the pads for 49.5 MHz case, and we have to lower + * the usdhc clock from 198 to 49.5 MHz to match the pad configuration. + * + * FIXME: This is should be removed after pinctrl API is available. + * At that time, usdhc driver can call pinctrl API to change pad + * configuration dynamically per different usdhc clock settings. + */ + clk_set_rate(&usdhc1_clk, 49500000); + clk_set_rate(&usdhc2_clk, 49500000); + clk_set_rate(&usdhc3_clk, 49500000); + clk_set_rate(&usdhc4_clk, 49500000); + np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"); base = of_iomap(np, 0); WARN_ON(!base); diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index ae57769..4b976f0 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -32,6 +32,7 @@ /* VENDOR SPEC register */ #define SDHCI_VENDOR_SPEC 0xC0 #define SDHCI_VENDOR_SPEC_SDIO_QUIRK 0x00000002 +#define SDHCI_WTMK_LVL 0x44 #define SDHCI_MIX_CTRL 0x48 /* @@ -476,6 +477,13 @@ static int __devinit sdhci_esdhc_imx_probe(struct platform_device *pdev) if (is_imx53_esdhc(imx_data)) imx_data->flags |= ESDHC_FLAG_MULTIBLK_NO_INT; + /* + * The imx6q ROM code will change the default watermark level setting + * to something insane. Change it back here. + */ + if (is_imx6q_usdhc(imx_data)) + writel(0x08100810, host->ioaddr + SDHCI_WTMK_LVL); + boarddata = &imx_data->boarddata; if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) { if (!host->mmc->parent->platform_data) {