From patchwork Fri Aug 26 19:21:57 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 111827 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 0D92FB6FA1 for ; Sat, 27 Aug 2011 05:12:07 +1000 (EST) Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Qx1ou-0006CL-Cg; Fri, 26 Aug 2011 19:12:00 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Qx1ot-0005Gj-UN; Fri, 26 Aug 2011 19:11:59 +0000 Received: from va3ehsobe010.messaging.microsoft.com ([216.32.180.30] helo=VA3EHSOBE010.bigfish.com) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Qx1oq-0005GQ-4o for linux-arm-kernel@lists.infradead.org; Fri, 26 Aug 2011 19:11:57 +0000 Received: from mail177-va3-R.bigfish.com (10.7.14.247) by VA3EHSOBE010.bigfish.com (10.7.40.12) with Microsoft SMTP Server id 14.1.225.22; Fri, 26 Aug 2011 19:11:53 +0000 Received: from mail177-va3 (localhost.localdomain [127.0.0.1]) by mail177-va3-R.bigfish.com (Postfix) with ESMTP id 5E2231A02D7; Fri, 26 Aug 2011 19:11:53 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h839h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail177-va3 (localhost.localdomain [127.0.0.1]) by mail177-va3 (MessageSwitch) id 1314385890205290_26187; Fri, 26 Aug 2011 19:11:30 +0000 (UTC) Received: from VA3EHSMHS029.bigfish.com (unknown [10.7.14.246]) by mail177-va3.bigfish.com (Postfix) with ESMTP id 62259320409; Fri, 26 Aug 2011 19:10:52 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS029.bigfish.com (10.7.99.39) with Microsoft SMTP Server (TLS) id 14.1.225.22; Fri, 26 Aug 2011 19:10:40 +0000 Received: from az33smr02.freescale.net (10.64.34.200) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server id 14.1.323.2; Fri, 26 Aug 2011 14:10:39 -0500 Received: from localhost.localdomain ([10.29.240.182]) by az33smr02.freescale.net (8.13.1/8.13.0) with ESMTP id p7QJAa0Z010921; Fri, 26 Aug 2011 14:10:37 -0500 (CDT) From: Fabio Estevam To: Subject: [PATCH 1/5] ARM: mx5: Allow CCM definitions to work on MX51 and MX53 Date: Fri, 26 Aug 2011 16:21:57 -0300 Message-ID: <1314386521-29351-1-git-send-email-fabio.estevam@freescale.com> X-Mailer: git-send-email 1.6.0.4 MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110826_151156_351287_A63D61B6 X-CRM114-Status: GOOD ( 14.35 ) X-Spam-Score: 0.1 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [216.32.180.30 listed in list.dnswl.org] 0.8 UPPERCASE_50_75 message body is 50-75% uppercase Cc: Fabio Estevam , kernel@pengutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org Allow CCM (Clock Control Module) definitions to work on MX51 and MX53 by checking the cpu type in run-time and using the appropriate register bases. Also, MX50 shares the same base addresses for these registers as MX53. Signed-off-by: Fabio Estevam --- arch/arm/mach-mx5/crm_regs.h | 136 ++++++++++++++++++++++------------------- 1 files changed, 73 insertions(+), 63 deletions(-) diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h index 5e11ba7..4385307 100644 --- a/arch/arm/mach-mx5/crm_regs.h +++ b/arch/arm/mach-mx5/crm_regs.h @@ -24,6 +24,16 @@ #define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR) #define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR) #define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR) +#define MX53_CORTEXA8_BASE MX53_IO_ADDRESS(MX53_ARM_BASE_ADDR) +#define MX53_GPC_BASE MX53_IO_ADDRESS(MX53_GPC_BASE_ADDR) + +#define MX5_CORTEXA8_BASE (cpu_is_mx51() ? MX51_CORTEXA8_BASE : \ + MX53_CORTEXA8_BASE) +#define MX5_GPC_BASE (cpu_is_mx51() ? MX51_GPC_BASE : \ + MX53_GPC_BASE) + +#define MX5_CCM_BASE (cpu_is_mx51() ? MX51_CCM_BASE : \ + MX53_CCM_BASE) /* PLL Register Offsets */ #define MXC_PLL_DP_CTL 0x00 @@ -81,42 +91,42 @@ #define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF /* Register addresses of CCM*/ -#define MXC_CCM_CCR (MX51_CCM_BASE + 0x00) -#define MXC_CCM_CCDR (MX51_CCM_BASE + 0x04) -#define MXC_CCM_CSR (MX51_CCM_BASE + 0x08) -#define MXC_CCM_CCSR (MX51_CCM_BASE + 0x0C) -#define MXC_CCM_CACRR (MX51_CCM_BASE + 0x10) -#define MXC_CCM_CBCDR (MX51_CCM_BASE + 0x14) -#define MXC_CCM_CBCMR (MX51_CCM_BASE + 0x18) -#define MXC_CCM_CSCMR1 (MX51_CCM_BASE + 0x1C) -#define MXC_CCM_CSCMR2 (MX51_CCM_BASE + 0x20) -#define MXC_CCM_CSCDR1 (MX51_CCM_BASE + 0x24) -#define MXC_CCM_CS1CDR (MX51_CCM_BASE + 0x28) -#define MXC_CCM_CS2CDR (MX51_CCM_BASE + 0x2C) -#define MXC_CCM_CDCDR (MX51_CCM_BASE + 0x30) -#define MXC_CCM_CHSCDR (MX51_CCM_BASE + 0x34) -#define MXC_CCM_CSCDR2 (MX51_CCM_BASE + 0x38) -#define MXC_CCM_CSCDR3 (MX51_CCM_BASE + 0x3C) -#define MXC_CCM_CSCDR4 (MX51_CCM_BASE + 0x40) -#define MXC_CCM_CWDR (MX51_CCM_BASE + 0x44) -#define MXC_CCM_CDHIPR (MX51_CCM_BASE + 0x48) -#define MXC_CCM_CDCR (MX51_CCM_BASE + 0x4C) -#define MXC_CCM_CTOR (MX51_CCM_BASE + 0x50) -#define MXC_CCM_CLPCR (MX51_CCM_BASE + 0x54) -#define MXC_CCM_CISR (MX51_CCM_BASE + 0x58) -#define MXC_CCM_CIMR (MX51_CCM_BASE + 0x5C) -#define MXC_CCM_CCOSR (MX51_CCM_BASE + 0x60) -#define MXC_CCM_CGPR (MX51_CCM_BASE + 0x64) -#define MXC_CCM_CCGR0 (MX51_CCM_BASE + 0x68) -#define MXC_CCM_CCGR1 (MX51_CCM_BASE + 0x6C) -#define MXC_CCM_CCGR2 (MX51_CCM_BASE + 0x70) -#define MXC_CCM_CCGR3 (MX51_CCM_BASE + 0x74) -#define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78) -#define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C) -#define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80) -#define MXC_CCM_CCGR7 (MX51_CCM_BASE + 0x84) - -#define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84) +#define MXC_CCM_CCR (MX5_CCM_BASE + 0x00) +#define MXC_CCM_CCDR (MX5_CCM_BASE + 0x04) +#define MXC_CCM_CSR (MX5_CCM_BASE + 0x08) +#define MXC_CCM_CCSR (MX5_CCM_BASE + 0x0C) +#define MXC_CCM_CACRR (MX5_CCM_BASE + 0x10) +#define MXC_CCM_CBCDR (MX5_CCM_BASE + 0x14) +#define MXC_CCM_CBCMR (MX5_CCM_BASE + 0x18) +#define MXC_CCM_CSCMR1 (MX5_CCM_BASE + 0x1C) +#define MXC_CCM_CSCMR2 (MX5_CCM_BASE + 0x20) +#define MXC_CCM_CSCDR1 (MX5_CCM_BASE + 0x24) +#define MXC_CCM_CS1CDR (MX5_CCM_BASE + 0x28) +#define MXC_CCM_CS2CDR (MX5_CCM_BASE + 0x2C) +#define MXC_CCM_CDCDR (MX5_CCM_BASE + 0x30) +#define MXC_CCM_CHSCDR (MX5_CCM_BASE + 0x34) +#define MXC_CCM_CSCDR2 (MX5_CCM_BASE + 0x38) +#define MXC_CCM_CSCDR3 (MX5_CCM_BASE + 0x3C) +#define MXC_CCM_CSCDR4 (MX5_CCM_BASE + 0x40) +#define MXC_CCM_CWDR (MX5_CCM_BASE + 0x44) +#define MXC_CCM_CDHIPR (MX5_CCM_BASE + 0x48) +#define MXC_CCM_CDCR (MX5_CCM_BASE + 0x4C) +#define MXC_CCM_CTOR (MX5_CCM_BASE + 0x50) +#define MXC_CCM_CLPCR (MX5_CCM_BASE + 0x54) +#define MXC_CCM_CISR (MX5_CCM_BASE + 0x58) +#define MXC_CCM_CIMR (MX5_CCM_BASE + 0x5C) +#define MXC_CCM_CCOSR (MX5_CCM_BASE + 0x60) +#define MXC_CCM_CGPR (MX5_CCM_BASE + 0x64) +#define MXC_CCM_CCGR0 (MX5_CCM_BASE + 0x68) +#define MXC_CCM_CCGR1 (MX5_CCM_BASE + 0x6C) +#define MXC_CCM_CCGR2 (MX5_CCM_BASE + 0x70) +#define MXC_CCM_CCGR3 (MX5_CCM_BASE + 0x74) +#define MXC_CCM_CCGR4 (MX5_CCM_BASE + 0x78) +#define MXC_CCM_CCGR5 (MX5_CCM_BASE + 0x7C) +#define MXC_CCM_CCGR6 (MX5_CCM_BASE + 0x80) +#define MXC_CCM_CCGR7 (MX5_CCM_BASE + 0x84) + +#define MXC_CCM_CMEOR (MX5_CCM_BASE + 0x84) /* Define the bits in register CCR */ #define MXC_CCM_CCR_COSC_EN (1 << 12) @@ -502,30 +512,30 @@ #define MXC_CCM_CCGRx_CG1_OFFSET 2 #define MXC_CCM_CCGRx_CG0_OFFSET 0 -#define MXC_DPTC_LP_BASE (MX51_GPC_BASE + 0x80) -#define MXC_DPTC_GP_BASE (MX51_GPC_BASE + 0x100) -#define MXC_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180) -#define MXC_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0) -#define MXC_PGC_IPU_BASE (MX51_GPC_BASE + 0x220) -#define MXC_PGC_VPU_BASE (MX51_GPC_BASE + 0x240) -#define MXC_PGC_GPU_BASE (MX51_GPC_BASE + 0x260) -#define MXC_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280) -#define MXC_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0) -#define MXC_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0) -#define MXC_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0) -#define MXC_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0) -#define MXC_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300) +#define MXC_DPTC_LP_BASE (MX5_GPC_BASE + 0x80) +#define MXC_DPTC_GP_BASE (MX5_GPC_BASE + 0x100) +#define MXC_DVFS_CORE_BASE (MX5_GPC_BASE + 0x180) +#define MXC_DPTC_PER_BASE (MX5_GPC_BASE + 0x1C0) +#define MXC_PGC_IPU_BASE (MX5_GPC_BASE + 0x220) +#define MXC_PGC_VPU_BASE (MX5_GPC_BASE + 0x240) +#define MXC_PGC_GPU_BASE (MX5_GPC_BASE + 0x260) +#define MXC_SRPG_NEON_BASE (MX5_GPC_BASE + 0x280) +#define MXC_SRPG_ARM_BASE (MX5_GPC_BASE + 0x2A0) +#define MXC_SRPG_EMPGC0_BASE (MX5_GPC_BASE + 0x2C0) +#define MXC_SRPG_EMPGC1_BASE (MX5_GPC_BASE + 0x2D0) +#define MXC_SRPG_MEGAMIX_BASE (MX5_GPC_BASE + 0x2E0) +#define MXC_SRPG_EMI_BASE (MX5_GPC_BASE + 0x300) /* CORTEXA8 platform */ -#define MXC_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0) -#define MXC_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4) -#define MXC_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8) -#define MXC_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC) -#define MXC_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10) -#define MXC_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14) -#define MXC_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18) -#define MXC_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20) -#define MXC_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24) +#define MXC_CORTEXA8_PLAT_PVID (MX5_CORTEXA8_BASE + 0x0) +#define MXC_CORTEXA8_PLAT_GPC (MX5_CORTEXA8_BASE + 0x4) +#define MXC_CORTEXA8_PLAT_PIC (MX5_CORTEXA8_BASE + 0x8) +#define MXC_CORTEXA8_PLAT_LPC (MX5_CORTEXA8_BASE + 0xC) +#define MXC_CORTEXA8_PLAT_NEON_LPC (MX5_CORTEXA8_BASE + 0x10) +#define MXC_CORTEXA8_PLAT_ICGC (MX5_CORTEXA8_BASE + 0x14) +#define MXC_CORTEXA8_PLAT_AMC (MX5_CORTEXA8_BASE + 0x18) +#define MXC_CORTEXA8_PLAT_NMC (MX5_CORTEXA8_BASE + 0x20) +#define MXC_CORTEXA8_PLAT_NMS (MX5_CORTEXA8_BASE + 0x24) /* DVFS CORE */ #define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00) @@ -547,11 +557,11 @@ #define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40) /* GPC */ -#define MXC_GPC_CNTR (MX51_GPC_BASE + 0x0) -#define MXC_GPC_PGR (MX51_GPC_BASE + 0x4) -#define MXC_GPC_VCR (MX51_GPC_BASE + 0x8) -#define MXC_GPC_ALL_PU (MX51_GPC_BASE + 0xC) -#define MXC_GPC_NEON (MX51_GPC_BASE + 0x10) +#define MXC_GPC_CNTR (MX5_GPC_BASE + 0x0) +#define MXC_GPC_PGR (MX5_GPC_BASE + 0x4) +#define MXC_GPC_VCR (MX5_GPC_BASE + 0x8) +#define MXC_GPC_ALL_PU (MX5_GPC_BASE + 0xC) +#define MXC_GPC_NEON (MX5_GPC_BASE + 0x10) #define MXC_GPC_PGR_ARMPG_OFFSET 8 #define MXC_GPC_PGR_ARMPG_MASK (3 << 8)