Message ID | 20181120092615.11680-1-Zhiqiang.Hou@nxp.com |
---|---|
Headers | show |
Series | PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs | expand |
On Tue, Nov 20, 2018 at 09:27:51AM +0000, Z.q. Hou wrote: > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > Add PCIe Gen4 controller DT bindings of NXP Layerscape SoCs. > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > --- > V2: > - Change to use the layerscape-pci.txt for PCIe Gen4 controller > dt-bindings Sorry someone suggested this, but it seems there's no point in having these in the same file. New IP block, do a new file. > > .../bindings/pci/layerscape-pci.txt | 57 +++++++++++++++++++ > MAINTAINERS | 8 +++ > 2 files changed, 65 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt > index 66df1e81e0b8..3ef8836b6e97 100644 > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt > @@ -1,4 +1,6 @@ > +==================================== > Freescale Layerscape PCIe controller > +==================================== > > This PCIe host controller is based on the Synopsys DesignWare PCIe IP > and thus inherits all the common properties defined in designware-pcie.txt. > @@ -58,3 +60,58 @@ Example: > <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, > <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; > }; > + > +=================================== > +NXP Layerscape PCIe Gen4 controller > +=================================== > + > +This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all > +the common properties defined in mobiveil-pcie.txt. > + > +Required properties: > +- compatible: should contain the platform identifier such as: > + "fsl,lx2160a-pcie" > +- reg: base addresses and lengths of the PCIe controller register blocks. > + "config_axi_slave": PCIe controller registers > + "csr_axi_slave": Bridge config registers Wouldn't 'config' and 'csr' be sufficient? And these should be listed under reg-names. > +- interrupts: A list of interrupt outputs of the controller. Must contain an > + entry for each entry in the interrupt-names property. > +- interrupt-names: It could include the following entries: > + "intr": The interrupt that is asserted for controller interrupts > + "aer": Asserted for aer interrupt when chip support the aer interrupt with > + none MSI/MSI-X/INTx mode,but there is interrupt line for aer. > + "pme": Asserted for pme interrupt when chip support the pme interrupt with > + none MSI/MSI-X/INTx mode,but there is interrupt line for pme. > +- dma-coherent: Indicates that the hardware IP block can ensure the coherency > + of the data transferred from/to the IP block. This can avoid the software > + cache flush/invalid actions, and improve the performance significantly. > +- msi-parent : See the generic MSI binding described in > + Documentation/devicetree/bindings/interrupt-controller/msi.txt. > + > +Example: > + > + pcie@3400000 { > + compatible = "fsl,lx2160a-pcie"; > + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ > + 0x80 0x00000000 0x0 0x00001000>; /* configuration space */ > + reg-names = "csr_axi_slave", "config_axi_slave"; The order should match what's defined above. Also, normally the config space would be the bigger region unless config accesses are windowed. > + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ > + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ > + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ > + interrupt-names = "aer", "pme", "intr"; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + apio-wins = <8>; > + ppio-wins = <8>; If these have specific values on your h/w, please specify above. > + dma-coherent; > + bus-range = <0x0 0xff>; > + msi-parent = <&its>; > + ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, > + <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, > + <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, > + <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; > + };
On Wed, Dec 5, 2018 at 4:38 PM Rob Herring <robh@kernel.org> wrote: > > On Tue, Nov 20, 2018 at 09:27:51AM +0000, Z.q. Hou wrote: > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > > > Add PCIe Gen4 controller DT bindings of NXP Layerscape SoCs. > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > --- > > V2: > > - Change to use the layerscape-pci.txt for PCIe Gen4 controller > > dt-bindings > > Sorry someone suggested this, but it seems there's no point in having > these in the same file. New IP block, do a new file. > > > > > .../bindings/pci/layerscape-pci.txt | 57 +++++++++++++++++++ > > MAINTAINERS | 8 +++ > > 2 files changed, 65 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > index 66df1e81e0b8..3ef8836b6e97 100644 > > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > @@ -1,4 +1,6 @@ > > +==================================== > > Freescale Layerscape PCIe controller > > +==================================== > > > > This PCIe host controller is based on the Synopsys DesignWare PCIe IP > > and thus inherits all the common properties defined in designware-pcie.txt. > > @@ -58,3 +60,58 @@ Example: > > <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, > > <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; > > }; > > + > > +=================================== > > +NXP Layerscape PCIe Gen4 controller > > +=================================== > > + > > +This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all > > +the common properties defined in mobiveil-pcie.txt. > > + > > +Required properties: > > +- compatible: should contain the platform identifier such as: > > + "fsl,lx2160a-pcie" > > +- reg: base addresses and lengths of the PCIe controller register blocks. > > + "config_axi_slave": PCIe controller registers > > + "csr_axi_slave": Bridge config registers > > Wouldn't 'config' and 'csr' be sufficient? And these should be listed > under reg-names. NM on the names. I see these are inherited. Rob
Hi Rob, Thanks a lot for your comments! > -----Original Message----- > From: Rob Herring <robh@kernel.org> > Sent: 2018年12月6日 6:39 > To: Z.q. Hou <zhiqiang.hou@nxp.com> > Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; > bhelgaas@google.com; mark.rutland@arm.com; > l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li > <leoyang.li@nxp.com>; lorenzo.pieralisi@arm.com; > catalin.marinas@arm.com; will.deacon@arm.com; Mingkai Hu > <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>; Xiaowei Bao > <xiaowei.bao@nxp.com> > Subject: Re: [PATCHv2 22/25] dt-bindings: pci: Add NXP Layerscape SoCs PCIe > Gen4 controller > > On Tue, Nov 20, 2018 at 09:27:51AM +0000, Z.q. Hou wrote: > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > > > Add PCIe Gen4 controller DT bindings of NXP Layerscape SoCs. > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > --- > > V2: > > - Change to use the layerscape-pci.txt for PCIe Gen4 controller > > dt-bindings > > Sorry someone suggested this, but it seems there's no point in having these in > the same file. New IP block, do a new file. Leo, can you help comment on this? I'm not sure which one is better. > > > > > .../bindings/pci/layerscape-pci.txt | 57 > +++++++++++++++++++ > > MAINTAINERS | 8 +++ > > 2 files changed, 65 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > index 66df1e81e0b8..3ef8836b6e97 100644 > > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > @@ -1,4 +1,6 @@ > > +==================================== > > Freescale Layerscape PCIe controller > > +==================================== > > > > This PCIe host controller is based on the Synopsys DesignWare PCIe IP > > and thus inherits all the common properties defined in designware-pcie.txt. > > @@ -58,3 +60,58 @@ Example: > > <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, > > <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; > > }; > > + > > +=================================== > > +NXP Layerscape PCIe Gen4 controller > > +=================================== > > + > > +This PCIe controller is based on the Mobiveil PCIe IP and thus > > +inherits all the common properties defined in mobiveil-pcie.txt. > > + > > +Required properties: > > +- compatible: should contain the platform identifier such as: > > + "fsl,lx2160a-pcie" > > +- reg: base addresses and lengths of the PCIe controller register blocks. > > + "config_axi_slave": PCIe controller registers > > + "csr_axi_slave": Bridge config registers > > Wouldn't 'config' and 'csr' be sufficient? And these should be listed under > reg-names. > > > +- interrupts: A list of interrupt outputs of the controller. Must > > +contain an > > + entry for each entry in the interrupt-names property. > > +- interrupt-names: It could include the following entries: > > + "intr": The interrupt that is asserted for controller interrupts > > + "aer": Asserted for aer interrupt when chip support the aer interrupt > with > > + none MSI/MSI-X/INTx mode,but there is interrupt line for aer. > > + "pme": Asserted for pme interrupt when chip support the pme interrupt > with > > + none MSI/MSI-X/INTx mode,but there is interrupt line for pme. > > +- dma-coherent: Indicates that the hardware IP block can ensure the > > +coherency > > + of the data transferred from/to the IP block. This can avoid the > > +software > > + cache flush/invalid actions, and improve the performance significantly. > > +- msi-parent : See the generic MSI binding described in > > + Documentation/devicetree/bindings/interrupt-controller/msi.txt. > > + > > +Example: > > + > > + pcie@3400000 { > > + compatible = "fsl,lx2160a-pcie"; > > + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers > */ > > + 0x80 0x00000000 0x0 0x00001000>; /* configuration space > */ > > + reg-names = "csr_axi_slave", "config_axi_slave"; > > The order should match what's defined above. Yes, will change the order above in next version. > > Also, normally the config space would be the bigger region unless config > accesses are windowed. Yes, config accesses are windowed. > > > + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER > interrupt */ > > + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt > */ > > + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller > interrupt */ > > + interrupt-names = "aer", "pme", "intr"; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + device_type = "pci"; > > + apio-wins = <8>; > > + ppio-wins = <8>; > > If these have specific values on your h/w, please specify above. Confirmed with our HW team that PCIe@3600000 and PCIe@3800000 have different window number, will update the window number in next version. > > > + dma-coherent; > > + bus-range = <0x0 0xff>; > > + msi-parent = <&its>; > > + ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 > 0x40000000>; > > + #interrupt-cells = <1>; > > + interrupt-map-mask = <0 0 0 7>; > > + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 > IRQ_TYPE_LEVEL_HIGH>, > > + <0000 0 0 2 &gic 0 0 GIC_SPI 110 > IRQ_TYPE_LEVEL_HIGH>, > > + <0000 0 0 3 &gic 0 0 GIC_SPI 111 > IRQ_TYPE_LEVEL_HIGH>, > > + <0000 0 0 4 &gic 0 0 GIC_SPI 112 > IRQ_TYPE_LEVEL_HIGH>; > > + }; Thanks, Zhiqiang
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> This patch set is aim to refactor the Mobiveil driver and add PCIe support for NXP Layerscape series SoCs integrated Mobiveil's PCIe Gen4 controller. Hou Zhiqiang (25): PCI: mobiveil: uniform the register accessors PCI: mobiveil: format the code without function change PCI: mobiveil: correct the returned error number PCI: mobiveil: remove flag MSI_FLAG_MULTI_PCI_MSI PCI: mobiveil: correct PCI base address in MEM/IO outbound windows PCI: mobiveil: replace the resource list iteration function PCI: mobiveil: use WIN_NUM_0 explicitly for CFG outbound window PCI: mobiveil: use the 1st inbound window for MEM inbound transactions PCI: mobiveil: correct inbound/outbound window setup routines PCI: mobiveil: fix the INTx process error PCI: mobiveil: only fix up the Class Code field PCI: mobiveil: move out the link up waiting from mobiveil_host_init PCI: mobiveil: move irq chained handler setup out of DT parse PCI: mobiveil: initialize Primary/Secondary/Subordinate bus number dt-bindings: pci: mobiveil: change gpio_slave and apb_csr to optional PCI: mobiveil: refactor Mobiveil PCIe Host Bridge IP driver PCI: mobiveil: fix the checking of valid device PCI: mobiveil: continue to initialize the host upon no PCIe link PCI: mobiveil: disabled IB and OB windows set by bootloader PCI: mobiveil: add Byte and Half-Word width register accessors PCI: mobiveil: make mobiveil_host_init can be used to re-init host dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller PCI: mobiveil: add PCIe Gen4 RC driver for NXP Layerscape SoCs arm64: dts: freescale: lx2160a: add pcie DT nodes arm64: defconfig: Enable CONFIG_PCI_LAYERSCAPE_GEN4 .../bindings/pci/layerscape-pci.txt | 57 ++ .../devicetree/bindings/pci/mobiveil-pcie.txt | 2 + MAINTAINERS | 10 +- .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 163 ++++ arch/arm64/configs/defconfig | 1 + drivers/pci/controller/Kconfig | 11 +- drivers/pci/controller/Makefile | 2 +- drivers/pci/controller/mobiveil/Kconfig | 34 + drivers/pci/controller/mobiveil/Makefile | 5 + .../controller/mobiveil/pci-layerscape-gen4.c | 254 ++++++ .../controller/mobiveil/pcie-mobiveil-host.c | 628 +++++++++++++ .../controller/mobiveil/pcie-mobiveil-plat.c | 54 ++ .../pci/controller/mobiveil/pcie-mobiveil.c | 246 +++++ .../pci/controller/mobiveil/pcie-mobiveil.h | 222 +++++ drivers/pci/controller/pcie-mobiveil.c | 861 ------------------ 15 files changed, 1677 insertions(+), 873 deletions(-) create mode 100644 drivers/pci/controller/mobiveil/Kconfig create mode 100644 drivers/pci/controller/mobiveil/Makefile create mode 100644 drivers/pci/controller/mobiveil/pci-layerscape-gen4.c create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil-host.c create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil-plat.c create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil.c create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil.h delete mode 100644 drivers/pci/controller/pcie-mobiveil.c