Message ID | 1524855403-15301-1-git-send-email-aisheng.dong@nxp.com |
---|---|
Headers | show |
Series | clk: imx: add imx8qxp clock support | expand |
Hi, same functionality is actually needed on iMX7d and many other non NXP socs. IMO proper solution is to introduce generic clock proxy or some thing like this on top of rpmsg/virtio On Sat, Apr 28, 2018 at 02:56:31AM +0800, Dong Aisheng wrote: > This patch series adds i.MX8QXP clock support which is based > on the clock service provided by SCU firmware. > It depends on SCU APIs patch set. > > Dong Aisheng (12): > clk: imx: add configuration option for mmio clks > clk: imx: scu: add scu clock common part > clk: imx: scu: add scu clock divider > clk: imx: scu: add scu clock gpr divider > clk: imx: scu: add scu clock gate > clk: imx: scu: add scu clock gpr gate > clk: imx: scu: add scu clock mux > clk: imx: scu: add scu clock gpr mux > clk: imx: add common imx_clk_hw_fixed functions > clk: imx: add imx_check_clk_hws helper function > dt-bindings: clock: add imx8qxp clock binding doc > clk: imx: add imx8qxp clk driver > > .../devicetree/bindings/clock/imx8qxp-clk.txt | 39 ++ > arch/arm/mach-imx/Kconfig | 10 + > drivers/clk/Kconfig | 1 + > drivers/clk/imx/Kconfig | 7 + > drivers/clk/imx/Makefile | 4 +- > drivers/clk/imx/clk-common.h | 27 ++ > drivers/clk/imx/scu/Kconfig | 5 + > drivers/clk/imx/scu/Makefile | 12 + > drivers/clk/imx/scu/clk-divider-gpr-scu.c | 131 +++++++ > drivers/clk/imx/scu/clk-divider-scu.c | 129 +++++++ > drivers/clk/imx/scu/clk-gate-gpr-scu.c | 84 ++++ > drivers/clk/imx/scu/clk-gate-scu.c | 193 ++++++++++ > drivers/clk/imx/scu/clk-imx8qxp.c | 426 +++++++++++++++++++++ > drivers/clk/imx/scu/clk-mux-gpr-scu.c | 90 +++++ > drivers/clk/imx/scu/clk-mux-scu.c | 89 +++++ > drivers/clk/imx/scu/clk-scu.c | 25 ++ > drivers/clk/imx/scu/clk-scu.h | 97 +++++ > include/dt-bindings/clock/imx8qxp-clock.h | 362 +++++++++++++++++ > include/soc/imx/imx8qxp/lpcg.h | 186 +++++++++ > 19 files changed, 1916 insertions(+), 1 deletion(-) > create mode 100644 Documentation/devicetree/bindings/clock/imx8qxp-clk.txt > create mode 100644 drivers/clk/imx/Kconfig > create mode 100644 drivers/clk/imx/clk-common.h > create mode 100644 drivers/clk/imx/scu/Kconfig > create mode 100644 drivers/clk/imx/scu/Makefile > create mode 100644 drivers/clk/imx/scu/clk-divider-gpr-scu.c > create mode 100644 drivers/clk/imx/scu/clk-divider-scu.c > create mode 100644 drivers/clk/imx/scu/clk-gate-gpr-scu.c > create mode 100644 drivers/clk/imx/scu/clk-gate-scu.c > create mode 100644 drivers/clk/imx/scu/clk-imx8qxp.c > create mode 100644 drivers/clk/imx/scu/clk-mux-gpr-scu.c > create mode 100644 drivers/clk/imx/scu/clk-mux-scu.c > create mode 100644 drivers/clk/imx/scu/clk-scu.c > create mode 100644 drivers/clk/imx/scu/clk-scu.h > create mode 100644 include/dt-bindings/clock/imx8qxp-clock.h > create mode 100644 include/soc/imx/imx8qxp/lpcg.h > > -- > 2.7.4 > > >
On 01.05.2018 08:03, Oleksij Rempel wrote: > Hi, > > same functionality is actually needed on iMX7d and many other non NXP > socs. How is this needed on iMX7D? Afaik, on i.MX8QXP Linux does not have any direct access to the clock registers. It is all managed by SCU. However, on i.MX 7 Linux as is today accesses the clocks registers directly... > IMO proper solution is to introduce generic clock proxy or some thing > like this on top of rpmsg/virtio Given that NXP already used rpmsg in the past, I was wondering too why a new messaging mechanism had to be invented. Dong, do you know why? -- Stefan > > On Sat, Apr 28, 2018 at 02:56:31AM +0800, Dong Aisheng wrote: >> This patch series adds i.MX8QXP clock support which is based >> on the clock service provided by SCU firmware. >> It depends on SCU APIs patch set. >> >> Dong Aisheng (12): >> clk: imx: add configuration option for mmio clks >> clk: imx: scu: add scu clock common part >> clk: imx: scu: add scu clock divider >> clk: imx: scu: add scu clock gpr divider >> clk: imx: scu: add scu clock gate >> clk: imx: scu: add scu clock gpr gate >> clk: imx: scu: add scu clock mux >> clk: imx: scu: add scu clock gpr mux >> clk: imx: add common imx_clk_hw_fixed functions >> clk: imx: add imx_check_clk_hws helper function >> dt-bindings: clock: add imx8qxp clock binding doc >> clk: imx: add imx8qxp clk driver >> >> .../devicetree/bindings/clock/imx8qxp-clk.txt | 39 ++ >> arch/arm/mach-imx/Kconfig | 10 + >> drivers/clk/Kconfig | 1 + >> drivers/clk/imx/Kconfig | 7 + >> drivers/clk/imx/Makefile | 4 +- >> drivers/clk/imx/clk-common.h | 27 ++ >> drivers/clk/imx/scu/Kconfig | 5 + >> drivers/clk/imx/scu/Makefile | 12 + >> drivers/clk/imx/scu/clk-divider-gpr-scu.c | 131 +++++++ >> drivers/clk/imx/scu/clk-divider-scu.c | 129 +++++++ >> drivers/clk/imx/scu/clk-gate-gpr-scu.c | 84 ++++ >> drivers/clk/imx/scu/clk-gate-scu.c | 193 ++++++++++ >> drivers/clk/imx/scu/clk-imx8qxp.c | 426 +++++++++++++++++++++ >> drivers/clk/imx/scu/clk-mux-gpr-scu.c | 90 +++++ >> drivers/clk/imx/scu/clk-mux-scu.c | 89 +++++ >> drivers/clk/imx/scu/clk-scu.c | 25 ++ >> drivers/clk/imx/scu/clk-scu.h | 97 +++++ >> include/dt-bindings/clock/imx8qxp-clock.h | 362 +++++++++++++++++ >> include/soc/imx/imx8qxp/lpcg.h | 186 +++++++++ >> 19 files changed, 1916 insertions(+), 1 deletion(-) >> create mode 100644 Documentation/devicetree/bindings/clock/imx8qxp-clk.txt >> create mode 100644 drivers/clk/imx/Kconfig >> create mode 100644 drivers/clk/imx/clk-common.h >> create mode 100644 drivers/clk/imx/scu/Kconfig >> create mode 100644 drivers/clk/imx/scu/Makefile >> create mode 100644 drivers/clk/imx/scu/clk-divider-gpr-scu.c >> create mode 100644 drivers/clk/imx/scu/clk-divider-scu.c >> create mode 100644 drivers/clk/imx/scu/clk-gate-gpr-scu.c >> create mode 100644 drivers/clk/imx/scu/clk-gate-scu.c >> create mode 100644 drivers/clk/imx/scu/clk-imx8qxp.c >> create mode 100644 drivers/clk/imx/scu/clk-mux-gpr-scu.c >> create mode 100644 drivers/clk/imx/scu/clk-mux-scu.c >> create mode 100644 drivers/clk/imx/scu/clk-scu.c >> create mode 100644 drivers/clk/imx/scu/clk-scu.h >> create mode 100644 include/dt-bindings/clock/imx8qxp-clock.h >> create mode 100644 include/soc/imx/imx8qxp/lpcg.h >> >> -- >> 2.7.4 >> >> >> > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Tue, May 01, 2018 at 09:32:11AM +0200, Stefan Agner wrote: > On 01.05.2018 08:03, Oleksij Rempel wrote: > > Hi, > > > > same functionality is actually needed on iMX7d and many other non NXP > > socs. > > How is this needed on iMX7D? > > Afaik, on i.MX8QXP Linux does not have any direct access to the clock > registers. It is all managed by SCU. However, on i.MX 7 Linux as is > today accesses the clocks registers directly... iMX7D and iMX6SX provide access to same register set from Cortex A and Cortex M side. Since it is just dangerous to toggle same bits from two systems, only one should control it. After implementing imx_rproc driver and bringing up system on Cortex M4 side, we faced a problem of needing to properly control clocks and pins for other side. Clocks and pins should be configured only if some functionality is requested, so we can't just force defaults which will always work. I assume that only right solution for this problem is to introduce some generic clock-to-rpmsg, pinmux-to-rpmsg bridge. So far I know, many system vendors have same problem with different SoCs (Renesas, TI, ST, QCOM) and I assume it is a generic AMP issue. If each vendor will upstream firmware specific kernel side implementation to solve common problem, we will have tons on unmaintainable SoC/Firmware specific code. > > IMO proper solution is to introduce generic clock proxy or some thing > > like this on top of rpmsg/virtio > > Given that NXP already used rpmsg in the past, I was wondering too why a > new messaging mechanism had to be invented. > > Dong, do you know why? > > -- > Stefan > > > > > On Sat, Apr 28, 2018 at 02:56:31AM +0800, Dong Aisheng wrote: > >> This patch series adds i.MX8QXP clock support which is based > >> on the clock service provided by SCU firmware. > >> It depends on SCU APIs patch set. > >> > >> Dong Aisheng (12): > >> clk: imx: add configuration option for mmio clks > >> clk: imx: scu: add scu clock common part > >> clk: imx: scu: add scu clock divider > >> clk: imx: scu: add scu clock gpr divider > >> clk: imx: scu: add scu clock gate > >> clk: imx: scu: add scu clock gpr gate > >> clk: imx: scu: add scu clock mux > >> clk: imx: scu: add scu clock gpr mux > >> clk: imx: add common imx_clk_hw_fixed functions > >> clk: imx: add imx_check_clk_hws helper function > >> dt-bindings: clock: add imx8qxp clock binding doc > >> clk: imx: add imx8qxp clk driver > >> > >> .../devicetree/bindings/clock/imx8qxp-clk.txt | 39 ++ > >> arch/arm/mach-imx/Kconfig | 10 + > >> drivers/clk/Kconfig | 1 + > >> drivers/clk/imx/Kconfig | 7 + > >> drivers/clk/imx/Makefile | 4 +- > >> drivers/clk/imx/clk-common.h | 27 ++ > >> drivers/clk/imx/scu/Kconfig | 5 + > >> drivers/clk/imx/scu/Makefile | 12 + > >> drivers/clk/imx/scu/clk-divider-gpr-scu.c | 131 +++++++ > >> drivers/clk/imx/scu/clk-divider-scu.c | 129 +++++++ > >> drivers/clk/imx/scu/clk-gate-gpr-scu.c | 84 ++++ > >> drivers/clk/imx/scu/clk-gate-scu.c | 193 ++++++++++ > >> drivers/clk/imx/scu/clk-imx8qxp.c | 426 +++++++++++++++++++++ > >> drivers/clk/imx/scu/clk-mux-gpr-scu.c | 90 +++++ > >> drivers/clk/imx/scu/clk-mux-scu.c | 89 +++++ > >> drivers/clk/imx/scu/clk-scu.c | 25 ++ > >> drivers/clk/imx/scu/clk-scu.h | 97 +++++ > >> include/dt-bindings/clock/imx8qxp-clock.h | 362 +++++++++++++++++ > >> include/soc/imx/imx8qxp/lpcg.h | 186 +++++++++ > >> 19 files changed, 1916 insertions(+), 1 deletion(-) > >> create mode 100644 Documentation/devicetree/bindings/clock/imx8qxp-clk.txt > >> create mode 100644 drivers/clk/imx/Kconfig > >> create mode 100644 drivers/clk/imx/clk-common.h > >> create mode 100644 drivers/clk/imx/scu/Kconfig > >> create mode 100644 drivers/clk/imx/scu/Makefile > >> create mode 100644 drivers/clk/imx/scu/clk-divider-gpr-scu.c > >> create mode 100644 drivers/clk/imx/scu/clk-divider-scu.c > >> create mode 100644 drivers/clk/imx/scu/clk-gate-gpr-scu.c > >> create mode 100644 drivers/clk/imx/scu/clk-gate-scu.c > >> create mode 100644 drivers/clk/imx/scu/clk-imx8qxp.c > >> create mode 100644 drivers/clk/imx/scu/clk-mux-gpr-scu.c > >> create mode 100644 drivers/clk/imx/scu/clk-mux-scu.c > >> create mode 100644 drivers/clk/imx/scu/clk-scu.c > >> create mode 100644 drivers/clk/imx/scu/clk-scu.h > >> create mode 100644 include/dt-bindings/clock/imx8qxp-clock.h > >> create mode 100644 include/soc/imx/imx8qxp/lpcg.h > >> > >> -- > >> 2.7.4 > >> > >> > >> > > > > _______________________________________________ > > linux-arm-kernel mailing list > > linux-arm-kernel@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel >
On Sat, Apr 28, 2018 at 02:56:42AM +0800, Dong Aisheng wrote: > Add imx8qxp clock binding doc. > > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: Sascha Hauer <kernel@pengutronix.de> > Cc: Fabio Estevam <fabio.estevam@nxp.com> > Cc: Stephen Boyd <sboyd@kernel.org> > Cc: Michael Turquette <mturquette@baylibre.com> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: devicetree@vger.kernel.org > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> > --- > .../devicetree/bindings/clock/imx8qxp-clk.txt | 39 +++ > include/dt-bindings/clock/imx8qxp-clock.h | 362 +++++++++++++++++++++ > 2 files changed, 401 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/imx8qxp-clk.txt > create mode 100644 include/dt-bindings/clock/imx8qxp-clock.h > > diff --git a/Documentation/devicetree/bindings/clock/imx8qxp-clk.txt b/Documentation/devicetree/bindings/clock/imx8qxp-clk.txt > new file mode 100644 > index 0000000..5e365d7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/imx8qxp-clk.txt > @@ -0,0 +1,39 @@ > +NXP i.MX8QXP Clocks Based on SCFW > +-------------------------------------------------------------------- > + > +Some i.MX SoCs contain a system controller that is responsible for > +providing clock control service for the IPs. Communication between > +the host processor running an OS and the system controller happens > +through a SCU protocol [1]. > + > +[1] Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt > + > +Required properties: > + > +- compatible: Should be "fsl,imx8qxp-clock". > +- #clock-cells: Should be <1>. There's no reason for this node. Just make the parent (SCU) a clock provider. > + > +The clock consumer should specify the desired clock by having the clock > +ID in its "clocks" phandle cell. > +See include/dt-bindings/clock/imx8qxp-clock.h > +for the full list of i.MX8QXP clock IDs. > + > +Examples: > + > +#include <dt-bindings/clock/imx8qxp-clock.h> > + > +clk: clk { > + compatible = "fsl,imx8qxp-clk"; > + #clock-cells = <1>; > +}; > + > +i2c0: i2c@5a800000 { > + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; > + reg = <0x0 0x5a800000 0x0 0x4000>; > + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-parent = <&gic>; > + clocks = <&clk IMX8QXP_I2C0_CLK>, > + <&clk IMX8QXP_I2C0_IPG_CLK>; > + clock-names = "per", "ipg"; > + ... > +};
> -----Original Message----- > From: Rob Herring [mailto:robh@kernel.org] > Sent: Tuesday, May 1, 2018 11:37 PM > To: A.s. Dong <aisheng.dong@nxp.com> > Cc: linux-clk@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > sboyd@kernel.org; mturquette@baylibre.com; shawnguo@kernel.org; Fabio > Estevam <fabio.estevam@nxp.com>; dl-linux-imx <linux-imx@nxp.com>; > kernel@pengutronix.de; Mark Rutland <mark.rutland@arm.com>; > devicetree@vger.kernel.org > Subject: Re: [PATCH 11/12] dt-bindings: clock: add imx8qxp clock binding doc > > On Sat, Apr 28, 2018 at 02:56:42AM +0800, Dong Aisheng wrote: > > Add imx8qxp clock binding doc. > > > > Cc: Shawn Guo <shawnguo@kernel.org> > > Cc: Sascha Hauer <kernel@pengutronix.de> > > Cc: Fabio Estevam <fabio.estevam@nxp.com> > > Cc: Stephen Boyd <sboyd@kernel.org> > > Cc: Michael Turquette <mturquette@baylibre.com> > > Cc: Rob Herring <robh+dt@kernel.org> > > Cc: Mark Rutland <mark.rutland@arm.com> > > Cc: devicetree@vger.kernel.org > > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> > > --- > > .../devicetree/bindings/clock/imx8qxp-clk.txt | 39 +++ > > include/dt-bindings/clock/imx8qxp-clock.h | 362 > +++++++++++++++++++++ > > 2 files changed, 401 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/clock/imx8qxp-clk.txt > > create mode 100644 include/dt-bindings/clock/imx8qxp-clock.h > > > > diff --git a/Documentation/devicetree/bindings/clock/imx8qxp-clk.txt > > b/Documentation/devicetree/bindings/clock/imx8qxp-clk.txt > > new file mode 100644 > > index 0000000..5e365d7 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/imx8qxp-clk.txt > > @@ -0,0 +1,39 @@ > > +NXP i.MX8QXP Clocks Based on SCFW > > +-------------------------------------------------------------------- > > + > > +Some i.MX SoCs contain a system controller that is responsible for > > +providing clock control service for the IPs. Communication between > > +the host processor running an OS and the system controller happens > > +through a SCU protocol [1]. > > + > > +[1] Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt > > + > > +Required properties: > > + > > +- compatible: Should be "fsl,imx8qxp-clock". > > +- #clock-cells: Should be <1>. > > There's no reason for this node. Just make the parent (SCU) a clock provider. > It can be done, but do I need to also remove other nodes like pinctrl, power domain in the same sub-nodes Of SCU? BTW i saw arm,scpi.txt also keep the clk node under scpi node. Documentation/devicetree/bindings/arm/arm,scpi.txt Seems like SCU like ARM SCPI is more like a protocol node while still needs different drivers to provide services. Regards Dong Aisheng > > + > > +The clock consumer should specify the desired clock by having the > > +clock ID in its "clocks" phandle cell. > > +See include/dt-bindings/clock/imx8qxp-clock.h > > +for the full list of i.MX8QXP clock IDs. > > + > > +Examples: > > + > > +#include <dt-bindings/clock/imx8qxp-clock.h> > > + > > +clk: clk { > > + compatible = "fsl,imx8qxp-clk"; > > + #clock-cells = <1>; > > +}; > > + > > +i2c0: i2c@5a800000 { > > + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; > > + reg = <0x0 0x5a800000 0x0 0x4000>; > > + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-parent = <&gic>; > > + clocks = <&clk IMX8QXP_I2C0_CLK>, > > + <&clk IMX8QXP_I2C0_IPG_CLK>; > > + clock-names = "per", "ipg"; > > + ... > > +};