| Message ID | 20230925080538.2894982-1-mika.westerberg@linux.intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | ata: ahci: Add Intel Alder Lake-P AHCI controller to low power chipsets list | expand |
On 2023/09/25 10:05, Mika Westerberg wrote: > Intel Alder Lake-P AHCI controller needs to be added to the mobile > chipsets list in order to have link power management enabled. Without > this the CPU cannot enter lower power C-states making idle power > consumption high. > > Cc: Koba Ko <koba.ko@canonical.com> > Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Looks OK, but given that there is a tendency of the low power stuff to be buggy, was this well tested ? Also, does this need a Fixes/CC stable tag ? If not, I will queue this for 6.7. > --- > drivers/ata/ahci.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c > index 08745e7db820..d96f80b6ff5d 100644 > --- a/drivers/ata/ahci.c > +++ b/drivers/ata/ahci.c > @@ -423,6 +423,7 @@ static const struct pci_device_id ahci_pci_tbl[] = { > { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power }, /* Comet Lake PCH RAID */ > /* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */ > { PCI_VDEVICE(INTEL, 0x4b63), board_ahci_low_power }, /* Elkhart Lake AHCI */ > + { PCI_VDEVICE(INTEL, 0x7ae2), board_ahci_low_power }, /* Alder Lake-P AHCI */ > > /* JMicron 360/1/3/5/6, match class to avoid IDE function */ > { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
Hi, On Mon, Sep 25, 2023 at 11:09:01AM +0200, Damien Le Moal wrote: > On 2023/09/25 10:05, Mika Westerberg wrote: > > Intel Alder Lake-P AHCI controller needs to be added to the mobile > > chipsets list in order to have link power management enabled. Without > > this the CPU cannot enter lower power C-states making idle power > > consumption high. > > > > Cc: Koba Ko <koba.ko@canonical.com> > > Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> > > Looks OK, but given that there is a tendency of the low power stuff to be buggy, > was this well tested ? Yes it was tested (Koba Cc'd can confirm this). We also confirmed from Intel AHCI folks that the ADL (and RPL) AHCI controllers fully support this configuration. > Also, does this need a Fixes/CC stable tag ? If not, I > will queue this for 6.7. Up to you :) Typically PCI ID additions can go to stable as well. No fixes tag needed, though (there is no commit that this one fixes). Thanks!
On 2023/09/25 11:13, Mika Westerberg wrote: > Hi, > > On Mon, Sep 25, 2023 at 11:09:01AM +0200, Damien Le Moal wrote: >> On 2023/09/25 10:05, Mika Westerberg wrote: >>> Intel Alder Lake-P AHCI controller needs to be added to the mobile >>> chipsets list in order to have link power management enabled. Without >>> this the CPU cannot enter lower power C-states making idle power >>> consumption high. >>> >>> Cc: Koba Ko <koba.ko@canonical.com> >>> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> >> >> Looks OK, but given that there is a tendency of the low power stuff to be buggy, >> was this well tested ? > > Yes it was tested (Koba Cc'd can confirm this). We also confirmed from > Intel AHCI folks that the ADL (and RPL) AHCI controllers fully support > this configuration. > >> Also, does this need a Fixes/CC stable tag ? If not, I >> will queue this for 6.7. > > Up to you :) Typically PCI ID additions can go to stable as well. No > fixes tag needed, though (there is no commit that this one fixes). OK. I will not add a CC stable for now. If requested, we can trivially backport this later. > > Thanks!
On Mon, Sep 25, 2023 at 5:27 PM Damien Le Moal <dlemoal@kernel.org> wrote: > > On 2023/09/25 11:13, Mika Westerberg wrote: > > Hi, > > > > On Mon, Sep 25, 2023 at 11:09:01AM +0200, Damien Le Moal wrote: > >> On 2023/09/25 10:05, Mika Westerberg wrote: > >>> Intel Alder Lake-P AHCI controller needs to be added to the mobile > >>> chipsets list in order to have link power management enabled. Without > >>> this the CPU cannot enter lower power C-states making idle power > >>> consumption high. > >>> > >>> Cc: Koba Ko <koba.ko@canonical.com> > >>> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> > >> > >> Looks OK, but given that there is a tendency of the low power stuff to be buggy, > >> was this well tested ? > > > > Yes it was tested (Koba Cc'd can confirm this). We also confirmed from > > Intel AHCI folks that the ADL (and RPL) AHCI controllers fully support > > this configuration. I verified on an ADL platform with odd and disk devices and they work fine. > > > >> Also, does this need a Fixes/CC stable tag ? If not, I > >> will queue this for 6.7. > > > > Up to you :) Typically PCI ID additions can go to stable as well. No > > fixes tag needed, though (there is no commit that this one fixes). > > OK. I will not add a CC stable for now. If requested, we can trivially backport > this later. > > > > > Thanks! > > -- > Damien Le Moal > Western Digital Research >
On Tue, Sep 26, 2023 at 12:55:05PM +0800, Koba Ko wrote: > On Mon, Sep 25, 2023 at 5:27 PM Damien Le Moal <dlemoal@kernel.org> wrote: > > > > On 2023/09/25 11:13, Mika Westerberg wrote: > > > Hi, > > > > > > On Mon, Sep 25, 2023 at 11:09:01AM +0200, Damien Le Moal wrote: > > >> On 2023/09/25 10:05, Mika Westerberg wrote: > > >>> Intel Alder Lake-P AHCI controller needs to be added to the mobile > > >>> chipsets list in order to have link power management enabled. Without > > >>> this the CPU cannot enter lower power C-states making idle power > > >>> consumption high. > > >>> > > >>> Cc: Koba Ko <koba.ko@canonical.com> > > >>> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> > > >> > > >> Looks OK, but given that there is a tendency of the low power stuff to be buggy, > > >> was this well tested ? > > > > > > Yes it was tested (Koba Cc'd can confirm this). We also confirmed from > > > Intel AHCI folks that the ADL (and RPL) AHCI controllers fully support > > > this configuration. > > I verified on an ADL platform with odd and disk devices and > they work fine. Thanks! @Damien, just checking whether this fell through cracks because I do not see it applied to libata.git next branches?
On 10/2/23 15:21, Mika Westerberg wrote: > On Tue, Sep 26, 2023 at 12:55:05PM +0800, Koba Ko wrote: >> On Mon, Sep 25, 2023 at 5:27 PM Damien Le Moal <dlemoal@kernel.org> wrote: >>> >>> On 2023/09/25 11:13, Mika Westerberg wrote: >>>> Hi, >>>> >>>> On Mon, Sep 25, 2023 at 11:09:01AM +0200, Damien Le Moal wrote: >>>>> On 2023/09/25 10:05, Mika Westerberg wrote: >>>>>> Intel Alder Lake-P AHCI controller needs to be added to the mobile >>>>>> chipsets list in order to have link power management enabled. Without >>>>>> this the CPU cannot enter lower power C-states making idle power >>>>>> consumption high. >>>>>> >>>>>> Cc: Koba Ko <koba.ko@canonical.com> >>>>>> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> >>>>> >>>>> Looks OK, but given that there is a tendency of the low power stuff to be buggy, >>>>> was this well tested ? >>>> >>>> Yes it was tested (Koba Cc'd can confirm this). We also confirmed from >>>> Intel AHCI folks that the ADL (and RPL) AHCI controllers fully support >>>> this configuration. >> >> I verified on an ADL platform with odd and disk devices and >> they work fine. > > Thanks! > > @Damien, just checking whether this fell through cracks because I do not > see it applied to libata.git next branches? Sorry about the delay. I was traveling and the suspend/resume fixes used all my bandwidth. Will queue this today. Do you want this for 6.7 or as a fix for 6.6 ? The latter is OK.
On 9/25/23 17:05, Mika Westerberg wrote: > Intel Alder Lake-P AHCI controller needs to be added to the mobile > chipsets list in order to have link power management enabled. Without > this the CPU cannot enter lower power C-states making idle power > consumption high. > > Cc: Koba Ko <koba.ko@canonical.com> > Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Applied to libata for-6.7. Thanks !
Hi, On Tue, Oct 03, 2023 at 09:49:20AM +0900, Damien Le Moal wrote: > On 10/2/23 15:21, Mika Westerberg wrote: > > On Tue, Sep 26, 2023 at 12:55:05PM +0800, Koba Ko wrote: > >> On Mon, Sep 25, 2023 at 5:27 PM Damien Le Moal <dlemoal@kernel.org> wrote: > >>> > >>> On 2023/09/25 11:13, Mika Westerberg wrote: > >>>> Hi, > >>>> > >>>> On Mon, Sep 25, 2023 at 11:09:01AM +0200, Damien Le Moal wrote: > >>>>> On 2023/09/25 10:05, Mika Westerberg wrote: > >>>>>> Intel Alder Lake-P AHCI controller needs to be added to the mobile > >>>>>> chipsets list in order to have link power management enabled. Without > >>>>>> this the CPU cannot enter lower power C-states making idle power > >>>>>> consumption high. > >>>>>> > >>>>>> Cc: Koba Ko <koba.ko@canonical.com> > >>>>>> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> > >>>>> > >>>>> Looks OK, but given that there is a tendency of the low power stuff to be buggy, > >>>>> was this well tested ? > >>>> > >>>> Yes it was tested (Koba Cc'd can confirm this). We also confirmed from > >>>> Intel AHCI folks that the ADL (and RPL) AHCI controllers fully support > >>>> this configuration. > >> > >> I verified on an ADL platform with odd and disk devices and > >> they work fine. > > > > Thanks! > > > > @Damien, just checking whether this fell through cracks because I do not > > see it applied to libata.git next branches? > > Sorry about the delay. I was traveling and the suspend/resume fixes used all my > bandwidth. Will queue this today. Do you want this for 6.7 or as a fix for 6.6 ? > The latter is OK. 6.7 is fine, thanks!
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index 08745e7db820..d96f80b6ff5d 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -423,6 +423,7 @@ static const struct pci_device_id ahci_pci_tbl[] = { { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power }, /* Comet Lake PCH RAID */ /* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */ { PCI_VDEVICE(INTEL, 0x4b63), board_ahci_low_power }, /* Elkhart Lake AHCI */ + { PCI_VDEVICE(INTEL, 0x7ae2), board_ahci_low_power }, /* Alder Lake-P AHCI */ /* JMicron 360/1/3/5/6, match class to avoid IDE function */ { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
Intel Alder Lake-P AHCI controller needs to be added to the mobile chipsets list in order to have link power management enabled. Without this the CPU cannot enter lower power C-states making idle power consumption high. Cc: Koba Ko <koba.ko@canonical.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> --- drivers/ata/ahci.c | 1 + 1 file changed, 1 insertion(+)