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Mon, 8 Feb 2021 09:59:09 -0800 Envelope-to: git@xilinx.com, michal.simek@xilinx.com, axboe@kernel.dk, p.zabel@pengutronix.de, robh+dt@kernel.org, linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Received: from [10.140.6.35] (port=55682 helo=xhdsaipava40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1l9AoW-0001aF-8t; Mon, 08 Feb 2021 09:59:08 -0800 From: Piyush Mehta To: , , CC: , , , , , , Piyush Mehta Subject: [PATCH V3 2/2] ata: ahci: ceva: Update the driver to support xilinx GT phy Date: Mon, 8 Feb 2021 23:33:56 +0530 Message-ID: <1612807436-5238-3-git-send-email-piyush.mehta@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1612807436-5238-1-git-send-email-piyush.mehta@xilinx.com> References: <1612807436-5238-1-git-send-email-piyush.mehta@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5593cc0b-5369-4761-2676-08d8cc5b47b2 X-MS-TrafficTypeDiagnostic: BYAPR02MB5320: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:7691; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2021 17:59:28.9053 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5593cc0b-5369-4761-2676-08d8cc5b47b2 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT028.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR02MB5320 Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org SATA controller used in Xilinx ZynqMP platform uses xilinx GT phy which has 4 GT lanes and can be used by 4 peripherals at a time. SATA controller uses 1 GT phy lane among the 4 GT lanes. To configure the GT lane for the SATA controller, the below sequence is expected. 1. Assert the SATA controller reset. 2. Configure the xilinx GT phy lane for SATA controller (phy_init). 3. De-assert the SATA controller reset. 4. Wait for PLL of the GT lane used by SATA to be locked (phy_power_on). The ahci_platform_enable_resources() by default does the phy_init() and phy_power_on() but the default sequence doesn't work with Xilinx platforms. Because of this reason, updated the driver to support the new sequence. Added cevapriv->rst check, for backward compatibility with the older sequence. If the reset controller is not available, then the SATA controller will configure with the older sequences. Signed-off-by: Piyush Mehta Acked-by: Michal Simek --- drivers/ata/ahci_ceva.c | 43 ++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 40 insertions(+), 3 deletions(-) diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c index b10fd4c..b980218 100644 --- a/drivers/ata/ahci_ceva.c +++ b/drivers/ata/ahci_ceva.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "ahci.h" /* Vendor Specific Register Offsets */ @@ -87,6 +88,7 @@ struct ceva_ahci_priv { u32 axicc; bool is_cci_enabled; int flags; + struct reset_control *rst; }; static unsigned int ceva_ahci_read_id(struct ata_device *dev, @@ -202,13 +204,48 @@ static int ceva_ahci_probe(struct platform_device *pdev) cevapriv->ahci_pdev = pdev; + cevapriv->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, + NULL); + if (IS_ERR(cevapriv->rst)) { + if (PTR_ERR(cevapriv->rst) != -EPROBE_DEFER) + dev_err(&pdev->dev, "failed to get reset: %ld\n", + PTR_ERR(cevapriv->rst)); + } + hpriv = ahci_platform_get_resources(pdev, 0); if (IS_ERR(hpriv)) return PTR_ERR(hpriv); - rc = ahci_platform_enable_resources(hpriv); - if (rc) - return rc; + if (!cevapriv->rst) { + rc = ahci_platform_enable_resources(hpriv); + if (rc) + return rc; + } else { + int i; + + rc = ahci_platform_enable_clks(hpriv); + if (rc) + return rc; + /* Assert the controller reset */ + reset_control_assert(cevapriv->rst); + + for (i = 0; i < hpriv->nports; i++) { + rc = phy_init(hpriv->phys[i]); + if (rc) + return rc; + } + + /* De-assert the controller reset */ + reset_control_deassert(cevapriv->rst); + + for (i = 0; i < hpriv->nports; i++) { + rc = phy_power_on(hpriv->phys[i]); + if (rc) { + phy_exit(hpriv->phys[i]); + return rc; + } + } + } if (of_property_read_bool(np, "ceva,broken-gen2")) cevapriv->flags = CEVA_FLAG_BROKEN_GEN2;