From patchwork Mon Mar 12 11:40:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Preetham Chandru Ramchandra X-Patchwork-Id: 884455 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-ide-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 400GKg1Cxjz9sSd for ; Mon, 12 Mar 2018 22:41:43 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751320AbeCLLll (ORCPT ); Mon, 12 Mar 2018 07:41:41 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:15397 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751303AbeCLLlk (ORCPT ); Mon, 12 Mar 2018 07:41:40 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Mon, 12 Mar 2018 04:41:48 -0700 Received: from HQMAIL106.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 12 Mar 2018 04:41:40 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 12 Mar 2018 04:41:40 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Mon, 12 Mar 2018 11:41:40 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1347.2 via Frontend Transport; Mon, 12 Mar 2018 11:41:40 +0000 Received: from pchandru-pc.nvidia.com (Not Verified[10.24.37.8]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 12 Mar 2018 04:41:40 -0700 From: Preetham Chandru Ramchandra To: , , , , CC: , , , , , , Preetham Ramchandra Subject: [PATCH V8 6/9] ata: ahci_tegra: disable devslp for Tegra124 Date: Mon, 12 Mar 2018 17:10:35 +0530 Message-ID: <1520854838-21779-7-git-send-email-pchandru@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1520854838-21779-1-git-send-email-pchandru@nvidia.com> References: <1520854838-21779-1-git-send-email-pchandru@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-ide-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org From: Preetham Ramchandra Tegra124 does not support devslp and it should be disabled. Signed-off-by: Preetham Chandru R Acked-by: Thierry Reding --- v8: * spelled out t124 as Tegra124 * changed u32 quirks to boolean supports_devslp * moved the aux register comments above platform_get_resource() --- drivers/ata/ahci_tegra.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c index 547a6f93922c..620cdd16ef2f 100644 --- a/drivers/ata/ahci_tegra.c +++ b/drivers/ata/ahci_tegra.c @@ -166,12 +166,14 @@ struct tegra_ahci_ops { struct tegra_ahci_soc { const char *const *supply_names; u32 num_supplies; + bool supports_devslp; const struct tegra_ahci_ops *ops; }; struct tegra_ahci_priv { struct platform_device *pdev; void __iomem *sata_regs; + void __iomem *sata_aux_regs; struct reset_control *sata_rst; struct reset_control *sata_oob_rst; struct reset_control *sata_cold_rst; @@ -181,6 +183,18 @@ struct tegra_ahci_priv { const struct tegra_ahci_soc *soc; }; +static void tegra_ahci_handle_quirks(struct ahci_host_priv *hpriv) +{ + struct tegra_ahci_priv *tegra = hpriv->plat_data; + u32 val; + + if (tegra->sata_aux_regs && !tegra->soc->supports_devslp) { + val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); + val &= ~SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT; + writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); + } +} + static int tegra124_ahci_init(struct ahci_host_priv *hpriv) { struct tegra_ahci_priv *tegra = hpriv->plat_data; @@ -401,6 +415,7 @@ static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv) val &= ~SATA_CONFIGURATION_0_CLK_OVERRIDE; writel(val, tegra->sata_regs + SATA_CONFIGURATION_0); + tegra_ahci_handle_quirks(hpriv); /* Unmask SATA interrupts */ @@ -446,6 +461,7 @@ static const struct tegra_ahci_ops tegra124_ahci_ops = { static const struct tegra_ahci_soc tegra124_ahci_soc = { .supply_names = tegra124_supply_names, .num_supplies = ARRAY_SIZE(tegra124_supply_names), + .supports_devslp = false, .ops = &tegra124_ahci_ops, }; @@ -488,6 +504,16 @@ static int tegra_ahci_probe(struct platform_device *pdev) if (IS_ERR(tegra->sata_regs)) return PTR_ERR(tegra->sata_regs); + /* + * AUX registers is optional. + */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + if (res) { + tegra->sata_aux_regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(tegra->sata_aux_regs)) + return PTR_ERR(tegra->sata_aux_regs); + } + tegra->sata_rst = devm_reset_control_get(&pdev->dev, "sata"); if (IS_ERR(tegra->sata_rst)) { dev_err(&pdev->dev, "Failed to get sata reset\n");