From patchwork Mon Feb 12 17:26:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Preetham Chandru Ramchandra X-Patchwork-Id: 872202 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-ide-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zgCKy2ZfYz9sBZ for ; Tue, 13 Feb 2018 04:27:50 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753033AbeBLR1r (ORCPT ); Mon, 12 Feb 2018 12:27:47 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:5076 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751379AbeBLR1q (ORCPT ); Mon, 12 Feb 2018 12:27:46 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Mon, 12 Feb 2018 09:27:50 -0800 Received: from HQMAIL108.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 12 Feb 2018 09:27:46 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 12 Feb 2018 09:27:46 -0800 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Mon, 12 Feb 2018 17:27:45 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server id 15.0.1347.2 via Frontend Transport; Mon, 12 Feb 2018 17:27:45 +0000 Received: from pchandru-pc.nvidia.com (Not Verified[10.24.37.8]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 12 Feb 2018 09:27:45 -0800 From: Preetham Chandru Ramchandra To: , , , , , CC: , , , , , Preetham Ramchandra Subject: [PATCH V7 5/7] ata: ahci_tegra: disable devslp for t124 Date: Mon, 12 Feb 2018 22:56:44 +0530 Message-ID: <1518456406-21564-6-git-send-email-pchandru@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1518456406-21564-1-git-send-email-pchandru@nvidia.com> References: <1518456406-21564-1-git-send-email-pchandru@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-ide-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org From: Preetham Ramchandra t124 does not support devslp and it should be disabled. Signed-off-by: Preetham Chandru R --- drivers/ata/ahci_tegra.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c index 6aaf8a4571c8..62f2afb54789 100644 --- a/drivers/ata/ahci_tegra.c +++ b/drivers/ata/ahci_tegra.c @@ -145,6 +145,10 @@ #define FUSE_SATA_CALIB 0x124 #define FUSE_SATA_CALIB_MASK 0x3 +enum { + NO_DEVSLP = (1 << 0), +}; + struct sata_pad_calibration { u8 gen1_tx_amp; u8 gen1_tx_peak; @@ -166,12 +170,14 @@ struct tegra_ahci_ops { struct tegra_ahci_soc { const char *const *supply_names; u32 num_supplies; + u32 quirks; struct tegra_ahci_ops ops; }; struct tegra_ahci_priv { struct platform_device *pdev; void __iomem *sata_regs; + void __iomem *sata_aux_regs; struct reset_control *sata_rst; struct reset_control *sata_oob_rst; struct reset_control *sata_cold_rst; @@ -181,6 +187,18 @@ struct tegra_ahci_priv { struct tegra_ahci_soc *soc_data; }; +static void tegra_ahci_handle_quirks(struct ahci_host_priv *hpriv) +{ + struct tegra_ahci_priv *tegra = hpriv->plat_data; + u32 val; + + if (tegra->sata_aux_regs && (tegra->soc_data->quirks & NO_DEVSLP)) { + val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); + val &= ~SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT; + writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); + } +} + static int tegra124_ahci_init(struct ahci_host_priv *hpriv) { struct tegra_ahci_priv *tegra = hpriv->plat_data; @@ -400,6 +418,7 @@ static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv) val &= ~SATA_CONFIGURATION_0_CLK_OVERRIDE; writel(val, tegra->sata_regs + SATA_CONFIGURATION_0); + tegra_ahci_handle_quirks(hpriv); /* Unmask SATA interrupts */ @@ -441,6 +460,7 @@ static const char *const tegra124_supply_names[] = { static const struct tegra_ahci_soc tegra124_ahci_soc_data = { .supply_names = tegra124_supply_names, .num_supplies = ARRAY_SIZE(tegra124_supply_names), + .quirks = NO_DEVSLP, .ops = { .init = tegra124_ahci_init, }, @@ -485,6 +505,15 @@ static int tegra_ahci_probe(struct platform_device *pdev) tegra->sata_regs = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(tegra->sata_regs)) return PTR_ERR(tegra->sata_regs); + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + /* + * Aux register is optional. + */ + if (res) { + tegra->sata_aux_regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(tegra->sata_aux_regs)) + return PTR_ERR(tegra->sata_aux_regs); + } tegra->sata_rst = devm_reset_control_get(&pdev->dev, "sata"); if (IS_ERR(tegra->sata_rst)) {