From patchwork Mon Jan 23 17:00:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 718691 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3v6d8h2ycmz9srZ for ; Tue, 24 Jan 2017 04:09:40 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="I7Z+4hIZ"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751472AbdAWRJf (ORCPT ); Mon, 23 Jan 2017 12:09:35 -0500 Received: from mail-wm0-f53.google.com ([74.125.82.53]:38824 "EHLO mail-wm0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751586AbdAWRJe (ORCPT ); Mon, 23 Jan 2017 12:09:34 -0500 Received: by mail-wm0-f53.google.com with SMTP id r144so165927727wme.1 for ; Mon, 23 Jan 2017 09:09:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VaEcPb8epkQ54nK3HBwY3922VqlqjjxvgCWx3XjYNFs=; b=I7Z+4hIZex+ZEaFijo9Asr8K+yWDt7nlftJ4wrvVEt39Ci4VGpHMzUvtdwuj+KJzUH kj8mia5hlDe2klLrme6qBdTeXcLhVhPzcoY3X/OLIUONMaJi1z/tvRQQl3Xc2Ejb7opD b5hRbBeByOyeBbaxnWkgOoCvGcFFMoBnm9rX97O73ovNJX5d05f8y9hVUvi4YkttEwc3 Upy4Qif8xfoCIRUrI7KSK4Kcs4h4LN23pfJ9k/ClMEeHiiMowb23PpNrXjiO1tX3MEic x3CIY0Dqolag6+2h3Th3/MBlxAN8pCBkJwbFtQzC6W82dL+rQ35Gv2wmk/PoQP5v+vju HD3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VaEcPb8epkQ54nK3HBwY3922VqlqjjxvgCWx3XjYNFs=; b=Tz2IFKz6M9TGCGhymLnVQTzzJCbEQBd77leWZ810AxZxAzQNbuxjOmOYo07hNZ2hyi vek3J6lrmYz87AZQREmjd5NeZS5kO3SMnzd8w5CJorlysosTSdrFkv7ULmZGBcXEq7ep 0hfa+47h/eMT05SuwOTucL+es9fzOIv0L1Oemp8Jjr8f7EkYeUdU/MgTx7IYqNXR4hPz EH54gAxnvQUH1KGdlo2pzJwphTCsnUx/b/em6ttN+37zKNSYwvOvU/jvOPKi/FxMR+K1 O0PmmN6WYeTuE4MgOFE20q3ohunLuVy3AV2VkX3GjZrpuc3sqzupN3d6x2M2dUBHudwz U+ZQ== X-Gm-Message-State: AIkVDXJ/6qzWhIqo44SvrisSLo7EvW+xpKAvk0G1qJPtaYDqKeo7TrULCSB2nmgeMxlkbkv4 X-Received: by 10.28.19.78 with SMTP id 75mr15954838wmt.108.1485190876641; Mon, 23 Jan 2017 09:01:16 -0800 (PST) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id l10sm12758910wrb.44.2017.01.23.09.01.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Jan 2017 09:01:15 -0800 (PST) From: Bartosz Golaszewski To: Kevin Hilman , Sekhar Nori , Patrick Titiano , Michael Turquette , Tejun Heo , Rob Herring , Mark Rutland , Russell King , David Lechner Cc: linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski Subject: [PATCH v6 10/14] sata: ahci-da850: add a workaround for controller instability Date: Mon, 23 Jan 2017 18:00:52 +0100 Message-Id: <1485190856-4711-11-git-send-email-bgolaszewski@baylibre.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1485190856-4711-1-git-send-email-bgolaszewski@baylibre.com> References: <1485190856-4711-1-git-send-email-bgolaszewski@baylibre.com> Sender: linux-ide-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org We have a use case with the da850 SATA controller where at PLL0 frequency of 456MHz (needed to properly service the LCD controller) the chip becomes unstable and the hardreset operation is ignored the first time 50% of times. The sata core driver already retries to resume the link because some controllers ignore writes to the SControl register, but just retrying the resume operation doesn't work - we need to issue he phy/wake reset again to make it work. Reimplement ahci_hardreset() in the driver and poke the controller a couple times before really giving up. Signed-off-by: Bartosz Golaszewski Acked-by: Tejun Heo --- drivers/ata/ahci_da850.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/ata/ahci_da850.c b/drivers/ata/ahci_da850.c index 11dd87e..0b2b1a4 100644 --- a/drivers/ata/ahci_da850.c +++ b/drivers/ata/ahci_da850.c @@ -16,7 +16,8 @@ #include #include "ahci.h" -#define DRV_NAME "ahci_da850" +#define DRV_NAME "ahci_da850" +#define HARDRESET_RETRIES 5 /* SATA PHY Control Register offset from AHCI base */ #define SATA_P0PHYCR_REG 0x178 @@ -76,6 +77,29 @@ static int ahci_da850_softreset(struct ata_link *link, return ret; } +static int ahci_da850_hardreset(struct ata_link *link, + unsigned int *class, unsigned long deadline) +{ + int ret, retry = HARDRESET_RETRIES; + bool online; + + /* + * In order to correctly service the LCD controller of the da850 SoC, + * we increased the PLL0 frequency to 456MHz from the default 300MHz. + * + * This made the SATA controller unstable and the hardreset operation + * does not always succeed the first time. Before really giving up to + * bring up the link, retry the reset a couple times. + */ + do { + ret = ahci_do_hardreset(link, class, deadline, &online); + if (online) + return ret; + } while (retry--); + + return ret; +} + static struct ata_port_operations ahci_da850_port_ops = { .inherits = &ahci_platform_ops, .softreset = ahci_da850_softreset, @@ -83,6 +107,8 @@ static struct ata_port_operations ahci_da850_port_ops = { * No need to override .pmp_softreset - it's only used for actual * PMP-enabled ports. */ + .hardreset = ahci_da850_hardreset, + .pmp_hardreset = ahci_da850_hardreset, }; static const struct ata_port_info ahci_da850_port_info = {