From patchwork Thu Jan 19 13:29:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 717094 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3v456b4vTRz9sxN for ; Fri, 20 Jan 2017 00:59:03 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="MwFI9aht"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752662AbdASN65 (ORCPT ); Thu, 19 Jan 2017 08:58:57 -0500 Received: from mail-wm0-f45.google.com ([74.125.82.45]:38426 "EHLO mail-wm0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751953AbdASN6z (ORCPT ); Thu, 19 Jan 2017 08:58:55 -0500 Received: by mail-wm0-f45.google.com with SMTP id r144so78386960wme.1 for ; Thu, 19 Jan 2017 05:58:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gjYAUx7cCSy+KrACbqFxG1BPaNYntYNoHa+KVUCPqgQ=; b=MwFI9ahteYl7ojLdqz37PDbhKNxyHlA4sdUBL/ZGw6rJJXokLhlZk98+gjFJEv5vti a4B9KMLoJ/UMLfStf+e8jAFmX5wvd1QEXepA1UD7Bll6Ca43Yr7n2xbT3zV9aPs6CBc3 LVAUw7LKUDF0qfXrimM2BOjVkO4Rnf+njLZQl+1lUbh/d8OGiWe990ahZ19BOOaoZV7L S6TDZ5oWJEtA91D7MwBoyZLdG1ZVJSqW5rGhNQGxgOqLyzk0ARaVdO49DKPvFIKZ+Q8y NqLW7B/uRCGE6d038PkckwJhlhvbdepCkfvl1OrhKC4bRbl5Io0uF1O/lpAsSFG3KKvQ NKLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gjYAUx7cCSy+KrACbqFxG1BPaNYntYNoHa+KVUCPqgQ=; b=HIj/8hohQG6/FYbjz0A9FtvvVvMWCqMjgdX8VeGdDc+7Ymef4nFwJo1OxlpA177Ll9 lc+/7RAdZZape0paRSKiWm6cBUcvvkM1KPVY5RzPQYiPFvt1yECpeOGIbKXlAUTJ6c9o fdcS+/A+RCuTkr32xFGVccEegWaZdX5m4h3sxaqB85ipJ9SJuvaKhny9oPnP1C+2y4QY nAhsrgE8j2Mw89NBbNS3qEqJ7AgjiWuERGef2vFanHnXAZheMTFOCexRaMTrDRaIEO1+ iPvr4T7R0dsJzJQP9kQE/hu5/yRrH+HxVwoQidAEIqxa9j67LTb5qhGgZgEbcFqVVf1e OzTA== X-Gm-Message-State: AIkVDXJ/aeZf9v8Oe6ajwf8QlwVLP38kG6uGWmYpGB3ZV28nUnZh1oJjZE7YlT0gLP91aLTz X-Received: by 10.223.165.17 with SMTP id i17mr9055891wrb.62.1484832605740; Thu, 19 Jan 2017 05:30:05 -0800 (PST) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id c202sm53251996wmd.10.2017.01.19.05.30.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 19 Jan 2017 05:30:05 -0800 (PST) From: Bartosz Golaszewski To: Kevin Hilman , Sekhar Nori , Patrick Titiano , Michael Turquette , Tejun Heo , Rob Herring , Mark Rutland , Russell King , David Lechner Cc: linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski Subject: [PATCH v4 10/14] sata: ahci-da850: add a workaround for controller instability Date: Thu, 19 Jan 2017 14:29:44 +0100 Message-Id: <1484832588-18413-11-git-send-email-bgolaszewski@baylibre.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1484832588-18413-1-git-send-email-bgolaszewski@baylibre.com> References: <1484832588-18413-1-git-send-email-bgolaszewski@baylibre.com> Sender: linux-ide-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org We have a use case with the da850 SATA controller where at PLL0 frequency of 456MHz (needed to properly service the LCD controller) the chip becomes unstable and the hardreset operation is ignored the first time 50% of times. The sata core driver already retries to resume the link because some controllers ignore writes to the SControl register, but just retrying the resume operation doesn't work - we need to issue he phy/wake reset again to make it work. Reimplement ahci_hardreset() in the driver and poke the controller a couple times before really giving up. Signed-off-by: Bartosz Golaszewski --- drivers/ata/ahci_da850.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/ata/ahci_da850.c b/drivers/ata/ahci_da850.c index 11dd87e..0b2b1a4 100644 --- a/drivers/ata/ahci_da850.c +++ b/drivers/ata/ahci_da850.c @@ -16,7 +16,8 @@ #include #include "ahci.h" -#define DRV_NAME "ahci_da850" +#define DRV_NAME "ahci_da850" +#define HARDRESET_RETRIES 5 /* SATA PHY Control Register offset from AHCI base */ #define SATA_P0PHYCR_REG 0x178 @@ -76,6 +77,29 @@ static int ahci_da850_softreset(struct ata_link *link, return ret; } +static int ahci_da850_hardreset(struct ata_link *link, + unsigned int *class, unsigned long deadline) +{ + int ret, retry = HARDRESET_RETRIES; + bool online; + + /* + * In order to correctly service the LCD controller of the da850 SoC, + * we increased the PLL0 frequency to 456MHz from the default 300MHz. + * + * This made the SATA controller unstable and the hardreset operation + * does not always succeed the first time. Before really giving up to + * bring up the link, retry the reset a couple times. + */ + do { + ret = ahci_do_hardreset(link, class, deadline, &online); + if (online) + return ret; + } while (retry--); + + return ret; +} + static struct ata_port_operations ahci_da850_port_ops = { .inherits = &ahci_platform_ops, .softreset = ahci_da850_softreset, @@ -83,6 +107,8 @@ static struct ata_port_operations ahci_da850_port_ops = { * No need to override .pmp_softreset - it's only used for actual * PMP-enabled ports. */ + .hardreset = ahci_da850_hardreset, + .pmp_hardreset = ahci_da850_hardreset, }; static const struct ata_port_info ahci_da850_port_info = {