From patchwork Mon Mar 2 12:48:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 445105 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id ED4271400D5 for ; Mon, 2 Mar 2015 23:49:33 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751537AbbCBMtP (ORCPT ); Mon, 2 Mar 2015 07:49:15 -0500 Received: from mail-wi0-f180.google.com ([209.85.212.180]:38732 "EHLO mail-wi0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754585AbbCBMst (ORCPT ); Mon, 2 Mar 2015 07:48:49 -0500 Received: by wiwh11 with SMTP id h11so14552374wiw.3 for ; Mon, 02 Mar 2015 04:48:47 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kvovdtFnWH19p172v5oX6fxunDvLtJcB7XTaSgFJhG4=; b=AyUjeGJyRp4SG7Lcyxah3nVOo7R9duXquu7M8dKpV0Mzxhz5QwYEWsJI6B1+x1HZAA vBPwNpQ2iIAVisbV+pPesn3wtVCdjrQIsP4o6B2QwuVzx33dY8/7DMgDLZoFdf/98tQN stXeIEbLnfdH5fL3Y3kGp2zihWlXQPyGlMk2gjTHS9kVKxyfxhtw/UkwvGOfB49JM8Vd 1G/JSl1CCXZlsX+PGocuOGEPLlDAN/psTCzDgGeOjxDnY+EMnmy7g5N5iHXNuhkpp86O wPSG0IcavA8r+J/LBlzc6+ZFTOaSSnSEorf1rwUUZ6Fa2bSSeKmi8XOPdZcb/TNJLIWJ zyYg== X-Gm-Message-State: ALoCoQmxjmU7vLh4OJuMi4d2bfb+Y6pEIUjG2vCSBSZ7CEAYTtKn+3+rJI9X9sDTA+cxg6b4rL/+ X-Received: by 10.180.82.129 with SMTP id i1mr34787703wiy.1.1425300527769; Mon, 02 Mar 2015 04:48:47 -0800 (PST) Received: from localhost.localdomain (cpc14-aztw22-2-0-cust189.18-1.cable.virginm.net. [82.45.1.190]) by mx.google.com with ESMTPSA id t9sm15910109wia.15.2015.03.02.04.48.45 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 02 Mar 2015 04:48:46 -0800 (PST) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, maxime.coquelin@st.com, patrice.chotard@st.com, srinivas.kandagatla@gmail.com, tj@kernel.org Cc: peter.griffin@linaro.org, lee.jones@linaro.org, linux-ide@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 2/3] ARM: DT: STi: STiH407: Add sata DT nodes. Date: Mon, 2 Mar 2015 12:48:38 +0000 Message-Id: <1425300519-13747-3-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1425300519-13747-1-git-send-email-peter.griffin@linaro.org> References: <1425300519-13747-1-git-send-email-peter.griffin@linaro.org> Sender: linux-ide-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org Now that the miphy28lp is upstream, we can add the sata dt nodes for stih407 family silicon. This has been tested on b2120 board J4 (sata0 channel). These nodes are disabled by default as a special mini pci-e to sata daughter board is required which isn't shipped with the board. Signed-off-by: Peter Griffin Acked-by: Lee Jones --- arch/arm/boot/dts/stih407-family.dtsi | 44 +++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index a57c06e..d526921 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -338,6 +338,50 @@ }; }; + sata0: sata@9b20000 { + compatible = "st,ahci"; + reg = <0x9b20000 0x1000>; + + interrupts = ; + interrupt-names = "hostc"; + + phys = <&phy_port0 PHY_TYPE_SATA>; + phy-names = "ahci_phy"; + + resets = <&powerdown STIH407_SATA0_POWERDOWN>, + <&softreset STIH407_SATA0_SOFTRESET>, + <&softreset STIH407_SATA0_PWR_SOFTRESET>; + reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; + + clock-names = "ahci_clk"; + clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; + + status = "disabled"; + }; + + sata1: sata@9b28000 { + compatible = "st,ahci"; + reg = <0x9b28000 0x1000>; + + interrupts = ; + interrupt-names = "hostc"; + + phys = <&phy_port1 PHY_TYPE_SATA>; + phy-names = "ahci_phy"; + + resets = <&powerdown STIH407_SATA1_POWERDOWN>, + <&softreset STIH407_SATA1_SOFTRESET>, + <&softreset STIH407_SATA1_PWR_SOFTRESET>; + reset-names = "pwr-dwn", + "sw-rst", + "pwr-rst"; + + clock-names = "ahci_clk"; + clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; + + status = "disabled"; + }; + st_dwc3: dwc3@8f94000 { compatible = "st,stih407-dwc3"; reg = <0x08f94000 0x1000>, <0x110 0x4>;