From patchwork Mon Jul 14 11:18:08 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 369582 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id E324A14009C for ; Mon, 14 Jul 2014 21:18:29 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754468AbaGNLSV (ORCPT ); Mon, 14 Jul 2014 07:18:21 -0400 Received: from mail-wi0-f174.google.com ([209.85.212.174]:48661 "EHLO mail-wi0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754601AbaGNLSN (ORCPT ); Mon, 14 Jul 2014 07:18:13 -0400 Received: by mail-wi0-f174.google.com with SMTP id d1so2333936wiv.7 for ; Mon, 14 Jul 2014 04:18:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OtCnAJ5KYbqcYgqRNaWOYF0G6hVEvd/BJvU2N2fLiy8=; b=UDC9d8WIAVL3JaLuxsDwjSM57nUK15SD/vmFNjOO7nrZ1oyvwE0sFDKvJSuZ1ZM4/R RKWHSRTLpwnz/4psgmXYjRkYvpKnmxAOPuIVVIOcxr4EagSGP0nt2KrQgxS7PpnqS14Z OgdjPOlH5NTMgA9NSqdtVapvY/p0zKD2WcmImm4pzK1WfNsP4gEuo+Fwmt4URVhlf45U WSsGftbgNuVcoFzegL73ScItd0sVvY6q3Lwmme3L/wlo8+M7IEduNViMakIjZhtBYLYH pVtnTYY3+2/dqsrv9IHMJ/VBQNIz7sF+nU5jLwPsY4/x/ctN9CRNpcnVrarW2htCUILv JcRA== X-Gm-Message-State: ALoCoQlL2TU/Ixtq8uNTXM6N6bsj69rji3l2fMfKmUY6OOm6nn/uF8fU9EUyncLKlfh2hxZzshWR X-Received: by 10.180.90.233 with SMTP id bz9mr23411551wib.42.1405336691243; Mon, 14 Jul 2014 04:18:11 -0700 (PDT) Received: from srini-ThinkPad-X1-Carbon-2nd.dlink.com (host-2-99-228-46.as13285.net. [2.99.228.46]) by mx.google.com with ESMTPSA id v14sm24830542wjw.38.2014.07.14.04.18.10 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 14 Jul 2014 04:18:10 -0700 (PDT) From: Srinivas Kandagatla To: Kishon Vijay Abraham I Cc: Grant Likely , Rob Herring , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-ide@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v4 2/2] phy: qcom: Add APQ8064 SATA PHY device tree bindings Date: Mon, 14 Jul 2014 12:18:08 +0100 Message-Id: <1405336688-32221-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1405336651-32135-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1405336651-32135-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-ide-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org This patch adds binding spec for Qualcomm AP8064 SATA PHY. Signed-off-by: Srinivas Kandagatla --- .../bindings/phy/qcom-apq8064-sata-phy.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom-apq8064-sata-phy.txt diff --git a/Documentation/devicetree/bindings/phy/qcom-apq8064-sata-phy.txt b/Documentation/devicetree/bindings/phy/qcom-apq8064-sata-phy.txt new file mode 100644 index 0000000..952f6c9 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom-apq8064-sata-phy.txt @@ -0,0 +1,24 @@ +Qualcomm APQ8064 SATA PHY Controller +------------------------------------ + +SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers. +Each SATA PHY controller should have its own node. + +Required properties: +- compatible: compatible list, contains "qcom,apq8064-sata-phy". +- reg: offset and length of the SATA PHY register set; +- #phy-cells: must be zero +- clocks: a list of phandles and clock-specifier pairs, one for each entry in + clock-names. +- clock-names: must be "cfg" for phy config clock. + +Example: + sata_phy: sata-phy@1b400000 { + compatible = "qcom,apq8064-sata-phy"; + reg = <0x1b400000 0x200>; + + clocks = <&gcc SATA_PHY_CFG_CLK>; + clock-names = "cfg"; + + #phy-cells = <0>; + };