From patchwork Tue Nov 26 07:01:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loc Ho X-Patchwork-Id: 294231 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 628BE2C00B1 for ; Tue, 26 Nov 2013 18:02:09 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754105Ab3KZHCH (ORCPT ); Tue, 26 Nov 2013 02:02:07 -0500 Received: from exprod5og107.obsmtp.com ([64.18.0.184]:55943 "HELO exprod5og107.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1754504Ab3KZHCD (ORCPT ); Tue, 26 Nov 2013 02:02:03 -0500 Received: from mail-pb0-f54.google.com ([209.85.160.54]) (using TLSv1) by exprod5ob107.postini.com ([64.18.4.12]) with SMTP ID DSNKUpRHarpXuA61acMg31LQfKJimSkv+PPQ@postini.com; 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Mon, 25 Nov 2013 23:02:01 -0800 (PST) Received: from localhost ([198.137.200.11]) by mx.google.com with ESMTPSA id so2sm78209339pbc.5.2013.11.25.23.02.01 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 25 Nov 2013 23:02:01 -0800 (PST) From: Loc Ho To: olof@lixom.net, tj@kernel.org, arnd@arndb.de Cc: linux-scsi@vger.kernel.org, linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jcm@redhat.com, patches@apm.com, Loc Ho , Tuan Phan , Suman Tripathi Subject: [PATCH v5 4/4] arm64: Add APM X-Gene SoC SATA host controller DTS entries Date: Tue, 26 Nov 2013 00:01:25 -0700 Message-Id: <1385449285-30764-5-git-send-email-lho@apm.com> X-Mailer: git-send-email 1.5.5 In-Reply-To: <1385449285-30764-4-git-send-email-lho@apm.com> References: <1385449285-30764-1-git-send-email-lho@apm.com> <1385449285-30764-2-git-send-email-lho@apm.com> <1385449285-30764-3-git-send-email-lho@apm.com> <1385449285-30764-4-git-send-email-lho@apm.com> Sender: linux-ide-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org arm64: Add APM X-Gene SoC SATA host controller and clock DTS entries Signed-off-by: Loc Ho Signed-off-by: Tuan Phan Signed-off-by: Suman Tripathi --- arch/arm64/boot/dts/apm-storm.dtsi | 81 ++++++++++++++++++++++++++++++++++++ 1 files changed, 81 insertions(+), 0 deletions(-) diff --git a/arch/arm64/boot/dts/apm-storm.dtsi b/arch/arm64/boot/dts/apm-storm.dtsi index f74c26a..fd8ff25 100644 --- a/arch/arm64/boot/dts/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm-storm.dtsi @@ -176,6 +176,51 @@ reg-names = "csr-reg"; clock-output-names = "eth8clk"; }; + + sata01clk: sata01clk@1f21c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "sata01clk"; + reg = <0x0 0x1f21c000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "sata01clk"; + status = "disabled"; + csr-offset = <0x4>; + csr-mask = <0x3f>; + enable-offset = <0x0>; + enable-mask = <0x3f>; + }; + + sata23clk: sata23clk@1f22c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "sata23clk"; + reg = <0x0 0x1f22c000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "sata23clk"; + status = "ok"; + csr-offset = <0x4>; + csr-mask = <0x3f>; + enable-offset = <0x0>; + enable-mask = <0x3f>; + }; + + sata45clk: sata45clk@1f23c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "sata45clk"; + reg = <0x0 0x1f23c000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "sata45clk"; + status = "ok"; + csr-offset = <0x4>; + csr-mask = <0x3f>; + enable-offset = <0x0>; + enable-mask = <0x3f>; + }; }; serial0: serial@1c020000 { @@ -224,5 +269,41 @@ apm-tx-boost-gain = <0x3 0x3 0x3 0x3 0x3 0x3>; apm-tx-eye-tuning = <0xa 0xa 0xa 0xc 0xc 0xc>; }; + + sata1: sata@1a000000 { + compatible = "apm,xgene-ahci-sgmii"; + reg = <0x0 0x1a000000 0x0 0x1000>, + <0x0 0x1f210000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <0x0 0x86 0x4>; + status = "disabled"; + clocks = <&sata01clk 0>; + phys = <&phy1 0>; + phy-names = "sata-6g"; + }; + + sata2: sata@1a400000 { + compatible = "apm,xgene-ahci-sgmii"; + reg = <0x0 0x1a400000 0x0 0x1000>, + <0x0 0x1f220000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <0x0 0x87 0x4>; + status = "ok"; + clocks = <&sata23clk 0>; + phys = <&phy2 0>; + phy-names = "sata-6g"; + }; + + sata3: sata@1a800000 { + compatible = "apm,xgene-ahci-pcie"; + reg = <0x0 0x1a800000 0x0 0x1000>, + <0x0 0x1f230000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <0x0 0x88 0x4>; + status = "ok"; + clocks = <&sata45clk 0>; + phys = <&phy3 0>; + phy-names = "sata-6g"; + }; }; };