From patchwork Thu Nov 14 21:39:13 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loc Ho X-Patchwork-Id: 291385 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id B872A2C00BC for ; Fri, 15 Nov 2013 08:39:54 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758112Ab3KNVjx (ORCPT ); Thu, 14 Nov 2013 16:39:53 -0500 Received: from exprod5og110.obsmtp.com ([64.18.0.20]:37302 "HELO exprod5og110.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1758091Ab3KNVjr (ORCPT ); Thu, 14 Nov 2013 16:39:47 -0500 Received: from mail-pb0-f54.google.com ([209.85.160.54]) (using TLSv1) by exprod5ob110.postini.com ([64.18.4.12]) with SMTP ID DSNKUoVDIcA8xzoJ1MicJz51bKC3/+xBQeVe@postini.com; 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Thu, 14 Nov 2013 13:39:44 -0800 (PST) Received: from localhost ([198.137.200.11]) by mx.google.com with ESMTPSA id oj6sm1471908pab.9.2013.11.14.13.39.43 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 14 Nov 2013 13:39:44 -0800 (PST) From: Loc Ho To: olof@lixom.net, tj@kernel.org, arnd@arndb.de Cc: linux-scsi@vger.kernel.org, linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jcm@redhat.com, Loc Ho , Tuan Phan , Suman Tripathi Subject: [PATCH v4 4/4] arm64: Add APM X-Gene SoC SATA DTS entries Date: Thu, 14 Nov 2013 14:39:13 -0700 Message-Id: <1384465153-29902-5-git-send-email-lho@apm.com> X-Mailer: git-send-email 1.5.5 In-Reply-To: <1384465153-29902-4-git-send-email-lho@apm.com> References: <1384465153-29902-1-git-send-email-lho@apm.com> <1384465153-29902-2-git-send-email-lho@apm.com> <1384465153-29902-3-git-send-email-lho@apm.com> <1384465153-29902-4-git-send-email-lho@apm.com> Sender: linux-ide-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org arm64: Add APM X-Gene SoC SATA host controller and clock DTS entries Signed-off-by: Loc Ho Signed-off-by: Tuan Phan Signed-off-by: Suman Tripathi Reviewed-by: Arnd Bergmann Reviewed-by: Olof Johansson --- arch/arm64/boot/dts/apm-storm.dtsi | 70 ++++++++++++++++++++++++++++++++++++ 1 files changed, 70 insertions(+), 0 deletions(-) diff --git a/arch/arm64/boot/dts/apm-storm.dtsi b/arch/arm64/boot/dts/apm-storm.dtsi index b29b465..14f3d5b 100644 --- a/arch/arm64/boot/dts/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm-storm.dtsi @@ -176,6 +176,36 @@ reg-names = "csr-reg"; clock-output-names = "eth8clk"; }; + + eth01clk: eth01clk@1f21c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "eth01clk"; + reg = <0x0 0x1f21c000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "eth01clk"; + }; + + eth23clk: eth23clk@1f22c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "eth23clk"; + reg = <0x0 0x1f22c000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "eth23clk"; + }; + + sata45clk: sata45clk@1f23c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "sata45clk"; + reg = <0x0 0x1f23c000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "sata45clk"; + }; }; serial0: serial@1c020000 { @@ -218,5 +248,45 @@ #phy-cells = <0>; status = "ok"; }; + + sata0: sata@1a000000 { + compatible = "apm,xgene-ahci"; + id = <0>; + reg = <0x0 0x1a000000 0x0 0x100000 + 0x0 0x1f210000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <0x0 0x86 0x4>; + clocks = <ð01clk 0>; + status = "na"; + phys = <&sataphy0>; + phy-names = "sataphy0"; + }; + + sata1: sata@1a400000 { + compatible = "apm,xgene-ahci"; + id = <1>; + reg = <0x0 0x1a400000 0x0 0x100000 + 0x0 0x1f220000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <0x0 0x87 0x4>; + clocks = <ð23clk 0>; + status = "ok"; + phys = <&sataphy1>; + phy-names = "sataphy1"; + }; + + sata2: sata@1a800000 { + compatible = "apm,xgene-ahci"; + id = <2>; + reg = <0x0 0x1a800000 0x0 0x100000 + 0x0 0x1f230000 0x0 0x10000 + 0x0 0x1f2d0000 0x0 0x10000 >; + interrupt-parent = <&gic>; + interrupts = <0x0 0x88 0x4>; + clocks = <&sata45clk 0>; + status = "ok"; + phys = <&sataphy2>; + phy-names = "sataphy2"; + }; }; };