From patchwork Tue Oct 30 16:01:32 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasanth Ananthan X-Patchwork-Id: 195526 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 707B82C0095 for ; Wed, 31 Oct 2012 03:01:56 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933899Ab2J3QBz (ORCPT ); Tue, 30 Oct 2012 12:01:55 -0400 Received: from mail-bk0-f46.google.com ([209.85.214.46]:60403 "EHLO mail-bk0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933893Ab2J3QBz (ORCPT ); Tue, 30 Oct 2012 12:01:55 -0400 Received: by mail-bk0-f46.google.com with SMTP id jk13so253640bkc.19 for ; Tue, 30 Oct 2012 09:01:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=MPKcHRV5arKQOeAJ5OYtC2kMPrpsPrDPBg4YXmDuRbQ=; b=L7jI25nWF3BJ4SWqWVwT4gn5Nce00cnnqNr+Dk5rNobVf1bDUPZC/MjYdBzoOi1jgU Rv/qk3Z6tOyPUyGAmaVeXtoD7V7nrjzhayTNVP3Nd1YzN9n3qLBJhUY8Efunbe11YtpW lyEpim4jBuOidzU33T8s3m/LL7rerDbt4KHN5d6QOhhUnYpR+EE2JQqpV8ODHXqusFvR +KuMCH42gWjblgnRtI+js9/vogtY4Q0v8UVldCiMqo17EUQCkbPpq85kZSLU8MFi+q6g IYfg5ZGhstq3arerKwoUqihy0+yOB5MmckTKKTW1s1CLusPPWNk/Ewr+9Mt1+TXymmYy kxsg== Received: by 10.205.135.20 with SMTP id ie20mr10621758bkc.16.1351612914201; Tue, 30 Oct 2012 09:01:54 -0700 (PDT) Received: from localhost.localdomain ([91.224.175.20]) by mx.google.com with ESMTPS id v14sm1522974bkv.10.2012.10.30.09.01.51 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 30 Oct 2012 09:01:53 -0700 (PDT) From: Vasanth Ananthan To: kgene.kim@samsung.com, jgarzik@pobox.com, linux@arm.linux.org.uk Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-ide@vger.kernel.org, thomas.abraham@linaro.org, Vasanth Ananthan , Vasanth Ananthan Subject: [PATCH v2 1/6] ARM: EXYNOS5: Clock settings for SATA and SATA PHY Date: Tue, 30 Oct 2012 17:01:32 +0100 Message-Id: <1351612897-14923-2-git-send-email-vasanthananthan@gmail.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1351612897-14923-1-git-send-email-vasanthananthan@gmail.com> References: <1351612897-14923-1-git-send-email-vasanthananthan@gmail.com> Sender: linux-ide-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org This patch adds neccessary clock entries for SATA, SATA PHY and I2C_SATAPHY Signed-off-by: Vasanth Ananthan --- arch/arm/mach-exynos/clock-exynos5.c | 21 ++++++++++++++++++--- 1 files changed, 18 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index c44ca1e..124c54f 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -651,15 +651,20 @@ static struct clk exynos5_init_clocks_off[] = { .ctrlbit = (1 << 15), }, { .name = "sata", - .devname = "ahci", + .devname = "exynos5-sata", + .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 6), }, { - .name = "sata_phy", + .name = "sata-phy", + .devname = "exynos5-sata-phy", + .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 24), }, { - .name = "sata_phy_i2c", + .name = "i2c", + .devname = "exynos5-sata-phy-i2c", + .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 25), }, { @@ -1226,6 +1231,16 @@ static struct clksrc_clk exynos5_clksrcs[] = { .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 }, }, { .clk = { + .name = "sclk_sata", + .devname = "exynos5-sata", + .enable = exynos5_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 24), + }, + .sources = &exynos5_clkset_aclk, + .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 24, .size = 1 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 20, .size = 4 }, + }, { + .clk = { .name = "sclk_gscl_wrap", .devname = "s5p-mipi-csis.0", .enable = exynos5_clksrc_mask_gscl_ctrl,