diff mbox series

[v2] i2c: cadence: Avoid fifo clear after start

Message ID 20240503094208.296834-1-sai.pavan.boddu@amd.com
State Accepted
Headers show
Series [v2] i2c: cadence: Avoid fifo clear after start | expand

Commit Message

Sai Pavan Boddu May 3, 2024, 9:42 a.m. UTC 
The Driver unintentionally programs ctrl reg to clear the fifo, which
happens after the start of transaction. Previously, this was not an issue
as it involved read-modified-write. However, this issue breaks i2c reads
on QEMU, as i2c-read is executed before guest starts programming control
register.

Fixes: ff0cf7bca630 ("i2c: cadence: Remove unnecessary register reads")
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
---
Changes for V2:
	Fix commit message.

 drivers/i2c/busses/i2c-cadence.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Andi Shyti May 3, 2024, 6:46 p.m. UTC | #1 
Hi Sai Pavan,

On Fri, May 03, 2024 at 03:12:08PM +0530, Sai Pavan Boddu wrote:
> The Driver unintentionally programs ctrl reg to clear the fifo, which
> happens after the start of transaction. Previously, this was not an issue
> as it involved read-modified-write. However, this issue breaks i2c reads
> on QEMU, as i2c-read is executed before guest starts programming control
> register.
> 
> Fixes: ff0cf7bca630 ("i2c: cadence: Remove unnecessary register reads")
> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
> Acked-by: Michal Simek <michal.simek@amd.com>

pushed to i2c/i2c-host-fixes.

I will send it for pull request next week as this week is already
too late and I want to see a few rounds of tests before asking
Wolfram to take it.

Thanks,
Andi
diff mbox series

Patch

diff --git a/drivers/i2c/busses/i2c-cadence.c b/drivers/i2c/busses/i2c-cadence.c
index 4bb7d6756947..2fce3e84ba64 100644
--- a/drivers/i2c/busses/i2c-cadence.c
+++ b/drivers/i2c/busses/i2c-cadence.c
@@ -633,6 +633,7 @@  static void cdns_i2c_mrecv(struct cdns_i2c *id)
 
 	if (hold_clear) {
 		ctrl_reg &= ~CDNS_I2C_CR_HOLD;
+		ctrl_reg &= ~CDNS_I2C_CR_CLR_FIFO;
 		/*
 		 * In case of Xilinx Zynq SOC, clear the HOLD bit before transfer size
 		 * register reaches '0'. This is an IP bug which causes transfer size