| Message ID | 20230330133953.21074-4-pmalgujar@marvell.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Andi Shyti |
| Headers | show |
| Series | i2c: thunderx: Marvell thunderx i2c changes | expand |
Hi Suneel and Piysh, On Thu, Mar 30, 2023 at 06:39:53AM -0700, Piyush Malgujar wrote: > From: Suneel Garapati <sgarapati@marvell.com> > > Status code 0xF0 refers to expiry of TWSI controller > access watchdog and needs bus monitor reset using MODE > register. > > Signed-off-by: Suneel Garapati <sgarapati@marvell.com> > Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com> > --- > drivers/i2c/busses/i2c-octeon-core.c | 8 ++++++++ > drivers/i2c/busses/i2c-octeon-core.h | 1 + > 2 files changed, 9 insertions(+) > > diff --git a/drivers/i2c/busses/i2c-octeon-core.c b/drivers/i2c/busses/i2c-octeon-core.c > index 7c49dc8ccbd2ef05fec675d282193b98f2b69835..3482db7165f243232937e0af148fe996858e9f2e 100644 > --- a/drivers/i2c/busses/i2c-octeon-core.c > +++ b/drivers/i2c/busses/i2c-octeon-core.c > @@ -187,6 +187,7 @@ static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c) > static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read) > { > u8 stat; > + u64 mode; > > /* > * This is ugly... in HLC mode the status is not in the status register > @@ -249,6 +250,13 @@ static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read) > case STAT_RXADDR_NAK: > case STAT_AD2W_NAK: > return -ENXIO; > + > + case STAT_WDOG_TOUT: > + mode = __raw_readq(i2c->twsi_base + MODE(i2c)); > + /* Set BUS_MON_RST to reset bus monitor */ > + mode |= BIT(3); Would be nice to have this masks all defined, but other than this: Acked-by: Andi Shyti <andi.shyti@kernel.org> Thanks, Andi > + octeon_i2c_writeq_flush(mode, i2c->twsi_base + MODE(i2c)); > + return -EIO; > default: > dev_err(i2c->dev, "unhandled state: %d\n", stat); > return -EIO; > diff --git a/drivers/i2c/busses/i2c-octeon-core.h b/drivers/i2c/busses/i2c-octeon-core.h > index 89d7d3bb8e30bd5787978d17d5a9b20ab0d41e22..a8d1bf9e89b8b0d21f52ff9f77f0ecf5263b5843 100644 > --- a/drivers/i2c/busses/i2c-octeon-core.h > +++ b/drivers/i2c/busses/i2c-octeon-core.h > @@ -72,6 +72,7 @@ > #define STAT_SLAVE_ACK 0xC8 > #define STAT_AD2W_ACK 0xD0 > #define STAT_AD2W_NAK 0xD8 > +#define STAT_WDOG_TOUT 0xF0 > #define STAT_IDLE 0xF8 > > /* TWSI_INT values */ > -- > 2.17.1 >
diff --git a/drivers/i2c/busses/i2c-octeon-core.c b/drivers/i2c/busses/i2c-octeon-core.c index 7c49dc8ccbd2ef05fec675d282193b98f2b69835..3482db7165f243232937e0af148fe996858e9f2e 100644 --- a/drivers/i2c/busses/i2c-octeon-core.c +++ b/drivers/i2c/busses/i2c-octeon-core.c @@ -187,6 +187,7 @@ static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c) static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read) { u8 stat; + u64 mode; /* * This is ugly... in HLC mode the status is not in the status register @@ -249,6 +250,13 @@ static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read) case STAT_RXADDR_NAK: case STAT_AD2W_NAK: return -ENXIO; + + case STAT_WDOG_TOUT: + mode = __raw_readq(i2c->twsi_base + MODE(i2c)); + /* Set BUS_MON_RST to reset bus monitor */ + mode |= BIT(3); + octeon_i2c_writeq_flush(mode, i2c->twsi_base + MODE(i2c)); + return -EIO; default: dev_err(i2c->dev, "unhandled state: %d\n", stat); return -EIO; diff --git a/drivers/i2c/busses/i2c-octeon-core.h b/drivers/i2c/busses/i2c-octeon-core.h index 89d7d3bb8e30bd5787978d17d5a9b20ab0d41e22..a8d1bf9e89b8b0d21f52ff9f77f0ecf5263b5843 100644 --- a/drivers/i2c/busses/i2c-octeon-core.h +++ b/drivers/i2c/busses/i2c-octeon-core.h @@ -72,6 +72,7 @@ #define STAT_SLAVE_ACK 0xC8 #define STAT_AD2W_ACK 0xD0 #define STAT_AD2W_NAK 0xD8 +#define STAT_WDOG_TOUT 0xF0 #define STAT_IDLE 0xF8 /* TWSI_INT values */